Top Design Engineer Jobs

Lead design, fabrication, installation, startup, and troubleshooting of custom machinery (CNC winders and driven equipment). Produce detailed SolidWorks/AutoCAD fabrication drawings, perform FEA, tolerance analysis, and calculations. Coordinate automation/PLC and hydraulics integration, manage vendors, prepare BOMs and technical packages, estimate costs, and oversee commissioning and maintenance as project lead.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

Lead digital IP and SoC-level integration for mixed-signal microcontrollers, develop RTL, and oversee verification and integration processes.

Design and validate board-level and subsystem electrical designs for server, storage, networking, and rack platforms. Duties include schematic development, component selection, power/signal integrity analysis, bring-up/debug, BOM and ECO support, cross-functional collaboration, and communicating technical status and risks.

Design, develop, test, validate, integrate, and maintain mission-critical workflow management and data integration systems. Build digital thread solutions, custom tooling, and analytics dashboards. Implement Jira/Confluence-based traceability, automate workflows with scripting, lead risk and change management, support production systems, and produce technical documentation and training.

Lead end-to-end verification for chassis and interconnect IPs, build scalable UVM/SystemVerilog testbenches, drive simulation/formal convergence and coverage closure, collaborate with architecture/design/software, mentor engineers, and ensure functional signoff and performance/power goals.

Own and develop Cadence-based RTL-to-GDS physical design flows for RDU chips. Maintain and enhance Genus/Innovus/Cerebrus toolflows, script automation (TCL/Perl/Python), collaborate with physical designers and tool vendors, and ensure compliance with advanced TSMC node design rules (3nm and below).

The role focuses on enabling efficient silicon development through design methodologies, process technology, mentoring engineers, and driving innovation in SoC designs.

The Associate Engineer will design, develop, and integrate mechanical systems for a fifth-generation business jet, ensuring compliance with specifications and collaborating with cross-functional teams.

Lead innovative aircraft design projects using advanced tools. Focus on systems engineering across disciplines from conceptual design to flight testing.

Develop and maintain advanced verification environments using SystemVerilog/UVM/OVM; design UVM agents and behavioral models; implement assertions and coverage; create random and directed tests; debug simulation failures and analyze coverage; collaborate with design teams on SoC/IP verification.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.

Drive verification from architecture/design to production silicon by developing scalable methodology, creating testbenches and portable tests, executing subsystem and full-chip verification, achieving coverage closure, and leading reviews toward sign-off, tapeout, and silicon bring-up.

Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.

The Senior Principal Engineer will define and develop system architectures for high-speed industrial products, collaborating closely with customers and stakeholders. Responsibilities include product definition, development, and support, along with participation in business development and technical troubleshooting.

Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.

Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and review test plans, develop test harnesses and sequences, run regressions and close code/functional coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs.

Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.

Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and execute test plans, develop testbenches and harnesses, run regressions, close coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for space-qualified ASICs.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.

Lead Design for Automation (DFA) through new product development, ensuring automation-ready designs. Provide senior manufacturing engineering support for automation, robotics, welding, assembly, tooling, and material handling. Act as SME for automation-critical processes, drive DFA standards and governance, lead PFMEAs and capability reviews, support plant transfers and startups, and apply Lean continuous improvement to reduce cost, risk, and variation.

Design Verification Engineer responsible for test planning, verification, debugging, adversarial testing, and writing verification environments using HVLs and methodologies (UVM/RVM/OVM). Works with RTL, assertions, code coverage, and simulation acceleration tools; strong communication and scripting skills required.