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2 Days Ago
Irvine, CA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
As a Sr. IC Layout Engineer at SpaceX, you will work on IC layout for space and ground infrastructure projects, managing chip floor plans, layout of RF and analog blocks, and performing critical design checks. You’ll collaborate with multidisciplinary teams and spearhead layout techniques to integrate advanced silicon technology.
2 Days Ago
Redmond, WA, USA
8,879 Employees
120K-170K Annually
Junior
8,879 Employees
120K-170K Annually
Junior
Aerospace • Other
The IC Layout Engineer at SpaceX will collaborate with integrated circuit designers on chip layout and perform tasks such as estimating schedules, executing design checks, and handling layout integration for advanced silicon technology aimed at space applications.
2 Days Ago
Bastrop, TX, USA
8,879 Employees
Junior
8,879 Employees
Junior
Aerospace • Other
The Engineering Specialist for Starlink will support the manufacturing and testing processes for the user terminal by executing product introduction builds, operating automated equipment, resolving production issues, and driving continuous improvement in product quality and cost management.
2 Days Ago
Star, TX, USA
8,879 Employees
95K-130K Annually
Entry level
8,879 Employees
95K-130K Annually
Entry level
Aerospace • Other
As a Starship Integration Engineer at SpaceX, you'll integrate propulsion, avionics, and structural components, design production lines, and ensure test-ready hardware delivery. You'll also troubleshoot issues and collaborate with various engineering and production teams to optimize efficiency.
2 Days Ago
Irvine, CA, USA
8,879 Employees
160K-220K Annually
Junior
8,879 Employees
160K-220K Annually
Junior
Aerospace • Other
As an IC Layout Engineer at SpaceX, you will design layouts for RF and analog circuit blocks, collaborate on chip floor plans, ensure design compliance through rule checks, and facilitate layout integration for silicon projects aimed at enhancing Starlink's capabilities. You will also evaluate new EDA tools and improve layout techniques for the team.
2 Days Ago
Irvine, CA, USA
8,879 Employees
170K-230K Annually
Senior level
8,879 Employees
170K-230K Annually
Senior level
Aerospace • Other
The Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer will develop and implement cutting-edge ASICs, overseeing timing closure, synthesis, and formal verification processes. Responsibilities include managing timing constraints, collaborating with multidisciplinary teams, and ensuring high-quality results throughout the design cycle, particularly for the Starlink project.
2 Days Ago
Bastrop, TX, USA
8,879 Employees
125K-175K Annually
Senior level
8,879 Employees
125K-175K Annually
Senior level
Aerospace • Other
As a Sr. Compliance Engineer at SpaceX, you will coordinate regulatory compliance for Starlink products, drive design validation and certification activities, and ensure all regulatory requirements are met for global market access. You will work with internal teams and external certification bodies to manage compliance testing and product qualification.
2 Days Ago
Redmond, WA, USA
8,879 Employees
Mid level
8,879 Employees
Mid level
Aerospace • Other
The Engineering Development Technician will assist in the manufacturing and development of SpaceX's Starlink payloads and satellites by supporting production engineering phases, rework efforts, and general production improvement projects.
2 Days Ago
Redmond, WA, USA
8,879 Employees
95K-130K Annually
Junior
8,879 Employees
95K-130K Annually
Junior
Aerospace • Other
As an Integration and Test Engineer at SpaceX, you will manage integration build flows and test operations for satellite systems. Your role includes evaluating designs for manufacturability, interfacing with engineers and technicians, and developing assembly procedures. You will ensure satellites meet mission goals and address non-conformances effectively.
2 Days Ago
Redmond, WA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
The Sr. DDR IP Design Engineer at SpaceX will develop and integrate Memory Controller IP for SoC designs, tackle integration issues, perform RTL design, and support silicon bring-up and verification processes. Collaboration with architects and engineers is essential to enhance the performance of Starlink's network.
2 Days Ago
Sunnyvale, CA, USA
8,879 Employees
170K-230K Annually
Senior level
8,879 Employees
170K-230K Annually
Senior level
Aerospace • Other
The Sr. DDR IP Design Engineer will focus on developing high-quality memory controller IP for SpaceX SoC designs. Responsibilities include RTL design, integration of Memory Controller/PHY IP core, troubleshooting, writing specifications, silicon bring-up, and functional verification. The role involves collaborating with various engineering teams to enhance Starlink's performance.
2 Days Ago
Irvine, CA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
The role involves the development and integration of Memory Controller IP for SpaceX SoCs, focusing on RTL design, synthesis, and timing analysis. Responsibilities include collaborating with cross-disciplinary teams, writing design specifications, supporting silicon bring-up, and driving functional verification and timing closure.
2 Days Ago
Redmond, WA, USA
8,879 Employees
160K-220K Annually
Mid level
8,879 Employees
160K-220K Annually
Mid level
Aerospace • Other
Develop next-generation RFICs for deployment in space and ground infrastructures. Responsibilities include simulating RF systems, deriving specifications, developing circuits and components, evaluating prototypes, and assisting in production testing.
2 Days Ago
Redmond, WA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
The Sr. MMIC Design Engineer at SpaceX will develop next-generation MMICs for space and ground infrastructures, working on RF system specifications, product development, circuit simulation, and performance evaluation. The engineer will collaborate with cross-disciplinary teams to ensure compatibility and efficiency in the design of MMIC products.
2 Days Ago
Star, TX, USA
8,879 Employees
Junior
8,879 Employees
Junior
Aerospace • Other
The Build Specialist in Booster Structures Engineering collaborates with the production team to enhance manufacturing processes, drive engineering excellence, manage tools for project schedules, resolve manufacturing issues, and implement standard practices for quality and efficiency.
2 Days Ago
Redmond, WA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
The Sr. Design Verification Engineer will be responsible for verifying digital ASICs and FPGAs, developing test plans, conducting regressions, and contributing to pre- and post-silicon validation efforts to ensure complex digital designs meet performance requirements.
2 Days Ago
Sunnyvale, CA, USA
8,879 Employees
170K-230K Annually
Senior level
8,879 Employees
170K-230K Annually
Senior level
Aerospace • Other
The Sr. Design Verification Engineer is responsible for verifying digital ASIC and/or FPGA designs, developing test plans, executing test sequences, and ensuring comprehensive validation of complex digital circuits. This role involves collaboration with cross-disciplinary teams to enhance the Starlink network's capabilities.
2 Days Ago
Star, TX, USA
8,879 Employees
95K-130K Annually
Junior
8,879 Employees
95K-130K Annually
Junior
Aerospace • Other
The Surface and Corrosion Engineer at SpaceX is responsible for ensuring robust designs and materials for high-performance flight hardware, particularly in corrosion-prone environments. They will troubleshoot, develop inspections, research protective coatings, and train staff on corrosion management practices, all aimed at ensuring the longevity and reusability of the rocket systems.
2 Days Ago
Irvine, CA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
The Sr. Design Verification Engineer will be responsible for verifying digital ASIC and FPGA designs at both block and system levels. This involves writing and reviewing test plans, executing tests, and ensuring code and functional coverage. The engineer will also contribute to pre-silicon verification and post-silicon validation while working collaboratively with cross-disciplinary teams.
2 Days Ago
Irvine, CA, USA
8,879 Employees
160K-220K Annually
Senior level
8,879 Employees
160K-220K Annually
Senior level
Aerospace • Other
Develop cutting-edge silicon for space and ground infrastructure, optimize Starlink network performance, collaborate with cross-disciplinary teams, improve design methodologies, resolve design issues
2 Days Ago
Redmond, WA, USA
8,879 Employees
160K-220K Annually
Mid level
8,879 Employees
160K-220K Annually
Mid level
Aerospace • Other
Seeking a motivated engineer to work on cutting-edge silicon design for space and ground infrastructures, enabling connectivity globally. Responsibilities include partition synthesis, physical design methodologies, collaboration with ASIC design team, and signoff closure. Must have 5+ years of industry experience in ASIC and physical design flow development.
2 Days Ago
Jacksonville, FL, USA
6,436 Employees
Senior level
6,436 Employees
Senior level
Automotive • Insurance
The Technical Digital Lead will enhance digital experiences for auto insurance customers through web-based and mobile-first applications. Responsibilities include defining a strategic roadmap, leading development and execution of digital strategies, managing teams, consulting stakeholders, monitoring IT service delivery, implementing agile development strategies, and ensuring integration across systems.
Top Benefits:
401-K
Dental Insurance
Disability Insurance
+13 More
2 Days Ago
Ann Arbor, MI, USA
500 Employees
Entry level
500 Employees
Entry level
Artificial Intelligence • Automotive • Robotics • Software • Transportation
Torc is seeking talent across multiple roles including Software Engineers, Embedded Engineers, Machine Learning Engineers, DevOps Engineers, and Engineering Leadership for their autonomous vehicle technology team.
Top Benefits:
401-K
401-K Matching
Company Equity
+33 More
2 Days Ago
Chicago, IL, USA
45,929 Employees
147K-200K Annually
Senior level
45,929 Employees
147K-200K Annually
Senior level
AdTech • Marketing Tech
The Senior Manager of Data Engineering will lead a team to deliver transformative data solutions for enterprise clients. Responsibilities include acting as a trusted advisor, advancing large-scale data platforms, mentoring team members, and ensuring high-quality deliverables through coding standards and reviews.
2 Days Ago
New York, NY, USA
45,929 Employees
147K-200K Annually
Senior level
45,929 Employees
147K-200K Annually
Senior level
AdTech • Marketing Tech
The Senior Manager of Data Engineering will lead teams to build and implement large-scale data platforms, leveraging Google Cloud technologies to drive digital transformation for clients. Responsibilities include client engagement, data integration, and mentoring team members, ensuring high-quality deliverables and aligning technology solutions with business goals.
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