Top Design Engineer Jobs

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Lead verification strategy and implementation for digital modem/PHY designs. Build SystemVerilog/UVM testbenches, create test plans, drive coverage closure, debug complex issues, support silicon bring-up, and collaborate cross-functionally to validate wireless systems.

Lead end-to-end verification of high-throughput, real-time digital pipelines. Build SystemVerilog/UVM verification environments, assertion-based checks, constrained-random tests, and formal properties. Model algorithms in MATLAB/Simulink or Python, support FPGA prototyping and silicon bring-up, analyze results to drive fixes, and collaborate across digital, optical, mixed-signal, and software teams. Mentor junior engineers and contribute to verification methodology and documentation.

Lead the design, testing, and sign-off of Scout's ADAS compute platform and related camera hardware. Define ECU requirements, integrate ADAS into vehicle E/E architecture, manage software release plans, flash and validate ECUs, support troubleshooting from development to production, and coordinate international teams while ensuring safety, regulatory, and continuous improvement.

The role involves defining and implementing test plans for SoC design verification, developing testbenches, debugging simulations, and mentoring junior engineers.

Design, build, and maintain test systems for rocket hardware testing. Collaborate with technicians to address real-world engineering challenges and meet testing deadlines.

The Senior Mechanical Engineer is responsible for designing high-speed automated machinery, guiding junior staff, and ensuring project success through effective communication and design expertise.

Lead development of the internal photonics PDK: create Python-based pcells, build and verify compact models for active/passive devices, automate parameter extraction from FDTD/FEM solvers, validate models against lab measurements, implement CI/regression testing, and own netlist extraction and connectivity logic to ensure accurate system-level simulation.

The Physical Design Timing Engineer will drive backend digital execution, focusing on timing constraints, analysis, and closure on advanced CMOS technologies. Responsibilities include STA sign-off, collaborating with multiple teams, managing timing complexities, and automating timing ECO generation.

Lead development of the internal photonics PDK and component library. Build Python-based pcells, create and validate compact models for active and passive devices, automate parameter extraction from electromagnetic solvers, and correlate models with lab measurements. Implement regression testing, CI pipelines, and robust netlist/connectivity logic to ensure layout, models, and simulations remain synchronized.

The Senior Platform Engineer will design automated solutions, support deployments, implement management tools, and enhance system performance and security in a hybrid role.

Develop digital design solutions for various industries, work on cross-functional teams, participate in product development, and verify designs using formal techniques.

The role involves verifying analog and digital circuits, creating test benches, and applying verification methodologies to ensure product quality. It includes scripting for data processing and collaborating with design teams to resolve issues.

The role involves physical design implementation of custom CPU designs, including synthesis, static timing analysis, verification, and collaborating to optimize CPU parameters. Leadership and communication skills are essential.

Develop verification infrastructure for AI accelerator IP blocks, create testbenches, mentor junior engineers, and debug across teams.

Responsible for substation physical design, project planning, client relations, and staff development. Requires strong technical and project management skills.

Design production tooling and equipment for aerospace, collaborating with teams on complex projects. Perform design analysis and manage project budgets and schedules.

Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.

As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.

As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.

The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.

Develop UVM testbenches and constrained-random/directed tests for mixed‑signal IP. Define verification plans and coverage, run RTL and gate‑level verification, debug failures, analyze coverage, and collaborate with design teams to review specs and improve verification methodology. Support mixed‑signal verification using Verilog analog models.

The Senior Engineer will develop solutions for mixed-signal and digital integrated circuits, working through the product development lifecycle while verifying designs using digital methodologies and simulation tools.

Design and analyze precision metal components and EMI board-level shields from concept through production. Create 3D CAD and 2D drawings, perform FEA/forming analysis, manage item data in Aras, lead new item releases, support manufacturability/DFMEA, and troubleshoot production issues while collaborating with sales, manufacturing, and customers.

Execute pre-silicon mixed-signal verification for high-speed wireline communications and clock/data paths. Build scalable AMS/DMS testbenches, automation, and behavioral models. Verify DUTs to datasheets and system use-cases, triage bugs with design and systems teams, and maintain tools, coverage, and constrained-random stimulus for tapeout readiness.