Join our North America Palladium and Protium HW Development team and help shape the future of system-level chip design verification. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence’s market-leading hardware emulation and FPGA prototyping platforms. You will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D — develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers’ most complex architectural and high-Speed Protocol challenges.
Key Responsibilities
- Customer Enablement & Solutions: Collaborate with frontline engineering teams and customers to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium platforms.
- Requirements & Feature Development: Define and develop customer-specific emulation and prototyping requirements, focusing heavily on leading edge high-speed interfaces and memory protocols (e.g., PCIe, CXL).
- Advanced Solutions Engineering: Drive the development of advanced acceleration FW + FPGA system solutions, establish robust verification methodologies, and support the operation and maintenance of Cadence emulation tools.
- Root-Cause Debugging: Triage and resolve complex, systemic issues across the hardware/software boundary, optimizing driver behavior, protocol compliance, and overall system stability.
- Evaluations & Benchmarking: Lead technical evaluations and develop high-performance benchmarks to demonstrate the competitive advantages of Cadence hardware platforms.
- Technical Presentation: Create and deliver impactful technical presentations, white papers, and product demonstrations for existing and prospective customers.
What You’ll Need
- BS with a minimum of 10 years of experience or MS with a minimum of 7 years of experience
- Strong fundamentals in digital design, computer architecture, and system‑level verification
- Have deep technical knowledge in a few of; Simulation (Advanced Testbench), Emulation (TBA & ICE) & FPGA Prototyping
- Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++
- Understanding of standard interconnect or IO protocols used in modern chip designs
- Good debugging skills using waveforms, logs, and protocol analyzers
- Ability to work across hardware and software boundaries.
- Excellent communication, and interpersonal skills, ability to work in an international environment
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- BS with minimum 10 years experience or MS with minimum 7 years experience
- Strong fundamentals in digital design, computer architecture, and system-level verification
- Deep technical knowledge in Simulation (advanced testbench), Emulation (TBA & ICE) and FPGA prototyping
- Experience with hardware description languages SystemVerilog or Verilog and/or C/C++
- Understanding of standard interconnect and I/O protocols used in modern chip designs (e.g., PCIe, CXL)
- Debugging skills using waveforms, logs, and protocol analyzers
- Ability to work across hardware and software boundaries, including driver/firmware optimization
- Excellent communication and interpersonal skills; ability to work in an international environment
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
