Top Design Engineer Jobs

22 Days AgoSaved
In-Office
Austin, TX, USA
150K-275K Annually
Mid level
150K-275K Annually
Mid level
Artificial Intelligence • Hardware • Software
As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.
Top Skills: PerlPythonSystemverilogTclUvm
22 Days AgoSaved
In-Office
Westborough, MA, USA
109K-161K Annually
Junior
109K-161K Annually
Junior
Artificial Intelligence • Automotive • Semiconductor
As a Design Verification Engineer, you will verify chip circuitry designs, collaborate with RTL engineers, and use various simulation tools to ensure designs meet specifications.
Top Skills: CadenceLinuxMentorPythonSynopsys VcsSystem VerilogVerilog
22 Days AgoSaved
In-Office
Westborough, MA, USA
109K-161K Annually
Junior
109K-161K Annually
Junior
Artificial Intelligence • Automotive • Semiconductor
The Design for Test Engineer assists in developing testability features for digital circuits, focusing on DFT structures and collaboration for product quality.
Top Skills: Digital Logic DesignEda ToolsHdl Languages (VerilogPythonShellTclVhdl)
22 Days AgoSaved
In-Office
Waltham, MA, USA
89K-170K Annually
Senior level
89K-170K Annually
Senior level
Healthtech
Lead design assurance for the Opal system, ensuring quality and regulatory compliance in medical devices. Mentor junior engineers and manage complex projects.
Top Skills: CadFmeaIec 62304Iso 13485Software Testing FrameworksStatic Code Analysis Tools
22 Days AgoSaved
Hybrid
3 Locations
Senior level
Senior level
Hardware • Software
Responsible for end-to-end functional verification of mixed-signal ASICs, developing verification plans, testbenches, coverage analysis, and collaborating with cross-functional teams.
Top Skills: HvlSystemverilogUvmVerilogVhdl
22 Days AgoSaved
Hybrid
3 Locations
Senior level
Senior level
Hardware • Software
The role involves functional verification of ASIC designs, including developing verification plans, testbenches, and collaborating with cross-functional teams to ensure high-quality outcomes.
Top Skills: Mixed-Signal IcsSystemverilogUvmVerilogVhdl
22 Days AgoSaved
Hybrid
3 Locations
5-1000M Annually
Senior level
5-1000M Annually
Senior level
Hardware • Software
The Design Verification Engineer will conduct end-to-end functional verification of custom mixed-signal ASICs, develop testbenches, and collaborate across teams to enhance verification processes.
Top Skills: AvmOvmSystemverilogUvmVeraVerilogVhdl
22 Days AgoSaved
Hybrid
3 Locations
Junior
Junior
Hardware • Software
The Design Verification Engineer will develop verification plans, perform ASIC functional verification, design UVM testbenches, and collaborate with cross-functional teams to improve verification processes.
Top Skills: AvmOvmSystemverilogUvmVeraVerilogVhdl
Reposted 22 Days AgoSaved
In-Office
Rockville, MD, USA
99K-165K Annually
Mid level
99K-165K Annually
Mid level
Greentech • Energy
Responsible for designing and developing mechanical systems, performing process calculations, overseeing system engineering processes, and ensuring compliance with technical specifications and project requirements.
Top Skills: CadMechanical Systems DesignThermal And Hydraulic Systems
Reposted 22 Days AgoSaved
In-Office
Santa Clara, CA, USA
172K-236K Annually
Expert/Leader
172K-236K Annually
Expert/Leader
Artificial Intelligence • Semiconductor • Manufacturing
Manage engineering teams to develop and characterize hardware technologies, resolve complex process issues, validate performance, and support cross-functional integration for advanced semiconductor and display manufacturing solutions.
Top Skills: Autocad
Reposted 22 Days AgoSaved
In-Office
Austin, TX, USA
122K-200K Annually
Mid level
122K-200K Annually
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
As a CPU Physical Design Automation Engineer, you will develop and support tools for backend physical design and analyze designs for performance and reliability.
Top Skills: CadenceEda ToolsMentor GraphicsPerlPythonRtl2GdsStatic Timing AnalysisSynopsysTclVlsi
Reposted 22 Days AgoSaved
In-Office
3 Locations
122K-232K Annually
Senior level
122K-232K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
The role involves providing technical support for PDKs, digital reference flows, and signoff methodologies, primarily using Cadence tools, while ensuring quality improvements and documentation. The engineer will facilitate ASIC designs, validate processes, and engage with customers for successful tape-outs.
Top Skills: Cadence EdaPerlPythonShell ScriptingTcl
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23 Days AgoSaved
In-Office
Waltham, MA, USA
89K-170K Annually
Senior level
89K-170K Annually
Senior level
Healthtech
Lead design assurance for the Opal HDx Mapping System, managing design control activities, risk management, and software quality initiatives while mentoring junior engineers.
Top Skills: Iec 62304Iso 13485Iso 14971Quality System RegulationsRisk ManagementSoftware Testing Frameworks
23 Days AgoSaved
In-Office
Arden Hills, MN, USA
102K-194K Annually
Expert/Leader
102K-194K Annually
Expert/Leader
Healthtech
The Principal Design Quality Engineer supports product design control integration, ensuring compliance with quality standards and regulatory requirements in medical device development.
Top Skills: Design ControlsIso 13485Iso 14971Risk Management
23 Days AgoSaved
In-Office or Remote
10 Locations
231K-323K Annually
Expert/Leader
231K-323K Annually
Expert/Leader
Aerospace
The Principal ASIC Design Verification Engineer leads verification strategies for complex ASICs in space communications, establishing methodologies, resolving technical issues, and mentoring teams.
Top Skills: System VerilogUvm
23 Days AgoSaved
In-Office or Remote
10 Locations
198K-277K Annually
Senior level
198K-277K Annually
Senior level
Aerospace
The Senior ASIC Verification Engineer leads verification of complex digital subsystems, develops UVM environments, drives coverage closure, and mentors junior engineers.
Top Skills: System VerilogUvm
23 Days AgoSaved
In-Office
Irvine, CA, USA
136K-201K Annually
Senior level
136K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
We are seeking a Timing/STA Engineer with expertise in timing constraints development and STA methodologies for intricate SoC designs. Responsibilities include developing timing constraints, conducting static timing analysis, automating STA processes, and collaborating with cross-functional teams for design optimization.
Top Skills: Eda ToolsPrimetimePythonSta ToolsTcl
23 Days AgoSaved
In-Office
Irvine, CA, USA
136K-201K Annually
Senior level
136K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Seeking an experienced ASIC synthesis and design engineer to develop timing constraints and implement ASIC front-end tasks, collaborating across teams for high-speed designs.
Top Skills: AsicFusion CompilerPythonStaTclVlsi
23 Days AgoSaved
In-Office
San Jose, CA, USA
110K-300K Annually
Senior level
110K-300K Annually
Senior level
Artificial Intelligence • Hardware • Information Technology • Software
The role involves defining and implementing test plans for SoC design verification, developing testbenches, debugging simulations, and mentoring junior engineers.
Top Skills: AmbaArmCC++MipiOvmPerlPythonRisc-VShell ScriptingSystem CSystem VerilogTclUvmVerilog
Reposted 23 Days AgoSaved
In-Office
Santa Clara, CA, USA
188K-325K Annually
Expert/Leader
188K-325K Annually
Expert/Leader
Semiconductor • Manufacturing
The Design Verification Engineer will verify CPU cores and subsystems, develop verification plans, and automate verification flows using various scripting languages.
Top Skills: AceArmAssemblyAxiCChiMipsPerlPythonRisc-VShellSystemverilogUvm
Reposted 23 Days AgoSaved
In-Office
Austin, TX, USA
153K-265K Annually
Senior level
153K-265K Annually
Senior level
Semiconductor • Manufacturing
The role involves verifying CPU cores and subsystems, developing verification strategies, writing test cases, and analyzing coverage reports.
Top Skills: AssemblyCFpgaPerlPythonShellSystemverilogUvm
Reposted 23 Days AgoSaved
In-Office or Remote
2 Locations
130K-160K Annually
Senior level
130K-160K Annually
Senior level
Other • Consulting
The Senior Electrical Engineer will lead the design of electrical systems for buildings, collaborate with multidisciplinary teams, mentor junior staff, and support business development while ensuring high-performance and sustainable outcomes.
Top Skills: Agi32AutocadAutodesk RevitEasy PowerElumtoolsMS OfficeSkm
Reposted 23 Days AgoSaved
Hybrid
Newark, DE, USA
Mid level
Mid level
Consulting
The Associate Highway Engineering Design Task Lead provides technical leadership and design oversight for highway engineering projects, managing tasks related to design criteria, pavement design, traffic control, utility coordination, and interdisciplinary reviews across transportation projects.
Top Skills: AutocadMicrostationOpenroads (Ord)
Reposted 23 Days AgoSaved
Hybrid
Charlotte, NC, USA
Mid level
Mid level
Energy • Utilities • Renewable Energy
The Project Engineer leads design efforts in natural gas distribution, mentoring junior engineers, coordinating teams, and ensuring technical accuracy and compliance while enhancing processes.
Top Skills: EngineeringNatural Gas Distribution Design
Reposted 23 Days AgoSaved
Hybrid
Philadelphia, PA, USA
Mid level
Mid level
Consulting
The Associate Highway Engineer will provide technical leadership on transportation projects, overseeing design criteria, pavement designs, and interdisciplinary coordination. Responsibilities include supervising design tasks, developing construction specifications, and ensuring adherence to quality procedures.
Top Skills: AutocadMicrostationOpenroads
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