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Top Design Engineer Jobs
The Staff Design Quality Assurance Engineer leads quality assurance and quality engineering activities in product development, ensuring compliance with medical device regulations. Responsibilities include overseeing quality assurance programs, reviewing documents, supporting risk management, collaborating with various teams, and generating regulatory documentation.
The Solution Design Project Engineer will lead design teams to create large-scale material handling solutions, manage MHE projects, and collaborate with stakeholders. Responsibilities include developing system concepts, generating proposal drawings, managing project engineering efforts, and ensuring compliance with project processes.
The Senior FPGA Design Engineer is responsible for developing novel signal processing algorithms for MIMO wireless networking products and will participate in all stages of the research and development process. This role includes digital design, RTL coding, FPGA synthesis, hardware verification, and collaboration with engineering teams.
The Senior RF Design Engineer will design and develop RF subsystems for Silvus’ StreamCaster products, including discrete circuitry and RFICs. Responsibilities include schematic capture, PCB layout, RF performance testing, ensuring EMI compliance, and troubleshooting production issues.
The Principal RF Design Engineer will design and develop the RF subsystem for the StreamCaster MANET product line. Responsibilities include RF front end architecture design, PCB layout, performance characterization, and troubleshooting. The role requires collaboration with a multidisciplinary team and ensures compliance with EMI regulations.
The Staff Hardware Design Engineer at PsiQuantum will own hardware designs for a quantum computer system, collaborating with cross-functional teams. Responsibilities include designing circuitry for high-speed data links, ensuring signal integrity, creating test setups, optimizing and debugging electronic components, and maintaining thorough documentation of hardware designs.
As a Principal Engineer-Design at Microchip, you will lead the development of PCIe Switch products, responsible for defining verification plans, utilizing advanced verification techniques, simulating designs, and supporting emulation and ASIC lab validation.
The Senior Design Assurance Engineer leads quality engineering for new medical device products, ensuring compliance with quality standards and effective risk management. Responsibilities include strategic quality planning, collaboration with cross-functional teams, mentoring product development teams, and conducting failure investigations. They also serve as a subject matter expert during audits and drive improvements in quality systems.
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The PHY Design Engineer will design low-power communication systems and develop micro-architecture and SystemVerilog RTL. Responsibilities include collaborating on product specifications, design verification, identifying bottlenecks, and providing guidance to teams on physical design and timing closure.
As a PHY Design Engineer/Lead, you will be responsible for developing low-power WiFi and BT/BLE micro-architecture and RTL design. You will work on digital signal processing engines, analyze design bottlenecks, and collaborate with verification teams on test plans and design tools.
The Digital IC Design Engineer will be responsible for creating micro-architecture and RTL implementation of digital systems focused on low-power DSPs and hardware accelerators for brain-computer interfaces. Responsibilities include design optimization, collaboration on silicon tests, and balancing power/performance while working with firmware engineers.
The Senior Design Verification Engineer will lead verification efforts for CPU designs, collaborating with designers and architects. Responsibilities include developing functional test plans, writing directed tests in C and SystemVerilog, analyzing coverage, and enhancing the verification environment utilizing various verification tools and methodologies.
The Technical Staff Engineer will work on the design of System on Chip (SoC) products, supporting data center solutions in a rapidly evolving technology space. Responsibilities include developing innovative products for big data storage and AI/ML applications while collaborating with a diverse team to drive industry technology leadership.
The Principal Engineer - Design will design complex digital integrated circuits, define feature sets, support emulation and ASIC validation, and collaborate with design teams to resolve technical issues. This role requires strong communication skills and understanding of storage protocols.
The Senior Physical Design Methodology Engineer will develop physical design methodologies for graphics processors and SoCs, focusing on unique solutions for complex design challenges. Responsibilities include participating in PPA experiments, automation for design analysis, and employing various design techniques such as floor planning and power distribution.
The role involves developing innovative physical design methodologies for GPU, CPU, and SOCs, focusing on optimizing power, performance, and area (PPA). The engineer will work on advanced design flows, chip assembly, and collaborate with partners to improve methodology for high-performance designs.
The Technical Staff Engineer is responsible for verifying ASIC implementations and conducting ASIC Design Audits. They will participate in RTL implementation, support post-layout timing closure, verify timing constraints, and perform Static Timing Analysis using industry-standard tools. The role requires collaboration with the design team and involves using tools like Genus and Tempus for effective implementation.
The Principal Engineer - Design will be responsible for designing complex digital integrated circuits, supporting validation and emulation, communicating with teams for issue resolution, and defining design features. They will work on ASIC design flows and utilize design and verification tools, as well as manage low power methodology.
As a Senior Applied LLM Engineer at NVIDIA, you will develop and optimize AI algorithms for chip design, design LLM-powered solutions, and leverage advanced machine learning technologies. Collaborating with a dynamic team, you will contribute to innovative AI applications and maintain high engineering standards.
As a Senior DFD Architect, you will develop silicon debug capabilities for GPUs, collaborating with multiple teams to enhance debug features. Your responsibilities include identifying inefficiencies, mentoring junior engineers, and verifying DFD hardware. You will leverage your experience in computer architecture and RTL development.
As a Senior C++ Software Engineer at NVIDIA, you will develop and support infrastructure tools for chip design verification and optimization. Your role involves crafting efficient software to streamline workflows for design teams, enhancing CAD tools with AI, and collaborating with engineers globally.
Develop and enhance C++ based software tools for RTL design productivity and quality. Collaborate with customers to improve chip design processes and refine CI/CD flows. Research software solutions for efficiency across architecture, hardware, and software teams.
As a Senior Physical Design Methodology Engineer at NVIDIA, you will develop methodologies for implementing graphics processors and SOCs. Key responsibilities include addressing complex physical design challenges, developing flows for chip design, and ensuring effective power and clock distribution.
The Senior Mixed-Signal Design Verification Engineer will verify design and implementation of SoCs and GPUs, focusing on mixed-signal CMOS circuit design, developing verification infrastructure, and ensuring design correctness. Collaboration with multi-functional teams is essential.
As a Senior Digital Design Verification Engineer, you'll verify the design and implementation of innovative SerDes IPs using advanced methodologies. Responsibilities include building functional models, defining verification scope, developing infrastructure, writing test plans, and collaborating with architects and verification teams to ensure design correctness.
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