Staff Analog Design Engineer

Reposted 20 Days Ago
Be an Early Applicant
Santa Clara, CA, USA
Hybrid
155K-250K Annually
Senior level
Artificial Intelligence • Machine Learning • Software
The Role
Design analog-mixed signal integrated circuits, optimize for low power performance, and collaborate on silicon bring up and debugging.
Summary Generated by Built In

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Role Overview

d-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out. You will drive design from schematic through silicon bring-up, guiding layout engineers working in deep sub-micron process nodes (7nm and below) and ensuring designs meet low-power performance targets across process-voltage-temperature corners. You will partner closely with layout engineers, backend/digital integration teams, and cross-site colleagues to deliver silicon-ready designs. This is a high-impact role for someone who wants to shape the analog foundations of state-of-the-art AI hardware.

What You Will Do
  • Design analog-mixed signal circuits using industry-standard tools such as Cadence and Synopsys

  • Develop schematic-level circuit designs and conduct system-level performance analysis

  • Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners

  • Guide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as needed

  • Partner with backend engineers to integrate design and layout, and provide circuit models to support backend verification

  • Support testboard design for silicon bring-up, bench debug, and characterization

  • Build scripts to support silicon bring-up and test feature validation

What You Will Bring
  • BS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)

  • Experience with schematic capture, SPICE simulation, and Monte Carlo simulation

  • Experience with circuit layout, extraction, and back-annotated simulation

  • Experience with channel modeling using MATLAB or similar tools

  • Strong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teams

  • Strong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environment

Preferred Qualifications

We'd be excited about candidates with deep expertise in any one of the following areas:

  • SerDes verification & characterization — building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)

  • Clocking & CDR — ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures

  • TX/RX datapath — high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures

  • Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Skills Required

  • Completed a BS/MS/PhD in Electrical Engineering
  • 7+ years of related professional experience
Am I A Good Fit?
beta
Get Personalized Job Insights.
Our AI-powered fit analysis compares your resume with a job listing so you know if your skills & experience align.

The Company
HQ: Santa Clara, CA
102 Employees

What We Do

d-Matrix is building a new way of doing datacenter AI inferencing using in-memory computing (IMC) techniques with chiplet level scale-out interconnects. Founded in 2019, d-Matrix has attacked the physics of memory-compute integration using innovative circuit techniques, ML tools, software and algorithms; solving the memory-compute integration problem, which is the final frontier in AI compute efficiency.

Similar Jobs

Samsung Semiconductor, Inc. Logo Samsung Semiconductor, Inc.

Staff Engineer

Semiconductor • Manufacturing
In-Office
San Jose, CA, USA
2298 Employees
157K-243K Annually

Elevate Semiconductor Logo Elevate Semiconductor

Design Engineer

Semiconductor • Manufacturing
In-Office
San Diego, CA, USA
34 Employees
145K-195K Annually

Lumentum Logo Lumentum

Staff Engineer

3D Printing • Marketing Tech • Design
In-Office
San Jose, CA, USA
3219 Employees
109K-155K Annually

Microchip Technology Inc. Logo Microchip Technology Inc.

Staff Engineer

Hardware • Semiconductor
In-Office
San Jose, CA, USA
13393 Employees
91K-232K Annually

Similar Companies Hiring

Hanover Park Thumbnail
Artificial Intelligence • Fintech • Software • Financial Services
New York, New York
42 Employees
Kepler  Thumbnail
Fintech • Software
New York, New York
6 Employees
Onshore Thumbnail
Artificial Intelligence • Fintech • Software • Financial Services
New York, New York
60 Employees

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account