Top Remote Design Engineer Jobs

Design and analyze high-speed analog/mixed-signal circuits, create layouts, develop testing plans, and support design methodologies for telecom networks.

Lead frontend technical direction for the Trellis design system: design and build a production component library, define accessibility and theming models, create tooling and migration pipelines (codemods, refactoring automation), leverage AI coding agents, mentor senior engineers, and partner with PM/UX to drive frontend architecture and adoption across product teams.

The Principal Digital Design Engineer will lead the design and implementation of digital systems, drive RTL development, and ensure quality control for chip designs, collaborating cross-functionally while addressing engineering challenges.

Design, audit, and support glass melting furnaces and refractories worldwide. Scope and manage design/repair projects, supervise construction and hot repairs, perform campaign life assessments, provide technical support, and ensure safety and budget adherence.

Lead and supervise highway design work: define scope, prepare budgets and schedules, provide technical direction, and produce calculations, drawings, procurement documents, design packages, and reports. Prepare requisitions, mentor designers and junior engineers, and coordinate deliverables for NYSDOT projects.

Lead highway, interchange, and street design for major NYSDOT projects using 3D modeling and CAD. Perform geometric and drainage design, work zone traffic control, construction staging, quantity calculations, and produce detailed calculations, drawings, reports, and procurement documents. Supervise and mentor engineers and designers, coordinate multidisciplinary teams, optimize plans using visualization, and manage budget and schedule elements.

Support sales as a pre-sales technical authority for Beeline Enterprise: solution VMS components, respond to RFPs, scope SOWs, lead technical reviews, collaborate on demos, hand off to implementation, and represent Beeline at events to increase win rates and ensure retention.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVA, apply constrained-random and directed tests, run simulations, triage failures, drive root-cause analysis, maintain coverage and regression suites, and collaborate with cross-functional teams through sign-off.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Design and deliver substation physical design deliverables: layouts, elevations, bills of material, conduit/equipment layouts, and calculations (grounding, cable/conduit/transformer sizing, lightning protection, bus bracing). Prepare specifications, manage project milestones, coordinate with clients and internal teams, support staff development, and ensure timely, on-budget project execution.

Develop innovative physical design methodologies for GPUs and SOCs, focusing on PPA improvements and collaboration across multiple teams. Use AI/ML to enhance design efficiency.

The Senior Engineer II will integrate and maintain systems, focusing on Linux administration, network configurations, and automation scripting while collaborating with various teams to ensure efficient and secure solutions.

The role involves leading the evolution of Seeq's frontend design system, enhancing component quality, and creating reusable application patterns for complex applications, with a strong focus on user workflows and collaboration with cross-functional teams.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

Develop and maintain system-level methodologies and automation tools for SOC/CPU creation. Improve front-end RTL integration and quality, perform design quality checks, and coordinate with ASIC, physical design, CAD, package, software, and DFT teams to enable efficient, scalable chip builds.

Design and verify FPGA-based modem and physical-layer implementations for space communications. Architect RTL for SoC FPGAs, implement DSP/modem functions, develop UVM/self-checking verification, perform timing closure and hardware bring-up, and support radiation-tolerant, high-reliability aerospace designs.

Lead verification strategy and execution for complex digital and mixed-signal designs. Architect UVM/SystemVerilog environments, develop advanced test benches, define coverage metrics, lead debug and post-silicon validation, mentor junior engineers, and drive methodology improvements while collaborating with design teams and customers.

Responsible for the design and implementation of radio networks for public safety projects, ensuring customer satisfaction and system acceptance through collaboration and technical execution.

Design and build a scalable, responsive UI; lead frontend architecture and optimization; apply UI/UX best practices; integrate with backend APIs; ensure high web performance and deploy user-facing features.

Designs and develops silicon photonics integrated circuits, managing the entire development process, including testing and analysis for cutting-edge photonic devices and systems-on-chip.

Lead all technical aspects of large HV substation projects, coordinate stakeholders, manage engineering tasks, and oversee design activities.

Lead end-to-end DFT/DFx strategy and hands-on implementation for AI inference ASICs: define DFT architecture, integrate into RTL and third-party IP, drive ATPG/BIST/scan verification through tapeout, partner with physical design and external vendors, and support silicon bring-up.

The role involves conducting data analysis for process improvement, leading initiatives, mentoring staff, and developing business cases using ROI models to enhance efficiency and reduce costs.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Build backend services and APIs that integrate commercial CAD platforms (Siemens NX, CATIA, SOLIDWORKS, Creo, Inventor) with cloud-native AI services. Translate CAD models into machine-readable data, automate engineering workflows in Python, manage assemblies, parts, configurations, and partner with research teams on Engineering AI.