Top Remote Design Engineer Jobs

As a Senior Fullstack Engineer, you'll contribute to backend development for Toast's New Ventures team, collaborating on architecture and launching MVPs while addressing unmet operator needs.

Design and build polished web experiences across PSA products by partnering with design, product, and engineering. Ship production features, build rapid prototypes, maintain design systems, mentor engineers on design best practices, and elevate craft and consistency across the product ecosystem.

Design and develop primary and secondary structural components for a next-generation UAV. Perform CAD modeling, hand calculations, limited FEA, generate drawings and documentation, support validation and testing, collaborate with cross-functional teams, and iterate hardware through manufacturing and flight tests.

Design and develop primary and secondary structural components for a next-generation UAV platform from concept through production. Create CAD models and drawings, perform hand calculations and basic FEA, collaborate with cross-functional teams for system integration, support structural testing and validation, resolve manufacturing and flight-test issues, and produce engineering documentation in compliance with aerospace standards.

Lead design and development of primary and secondary aircraft structures for next-gen UAVs. Own CAD/FEA-driven structural lifecycle, material selection (composites/metal), testing, integration, verification, and mentor junior engineers while ensuring manufacturability and compliance with aerospace standards.

Design and develop primary and secondary structural components for a next-generation UAV. Execute full design lifecycle, perform hand calculations and limited FEA, support structural validation and testing, produce drawings and documentation, and collaborate with cross-functional teams to ensure manufacturability and system integration.

Collaborate with product designers to implement modular, reusable React components and pixel-perfect UI across desktop and mobile. Build performant CSS-driven interactions, animations, and micro-interactions. Bridge front-end logic with design and maintain high polish across Vetcove's applications.

Develop and execute UVM/SystemVerilog-based verification for AR display integrated circuits. Build assertion-based testbenches, create and run verification plans with functional and code coverage, use Siemens Questa for simulation and debug, and automate verification flows while collaborating with digital, analog, software, and verification teams.

Remote 12-month contract RTL Design Engineer to own micro-architecture and RTL implementation for complex digital blocks. Requires SystemVerilog/Verilog expertise, memory controller and SoC integration experience, IP integration, multi-clock-domain design, and sign-off familiarity (CDC/RDC/lint/synthesis). Works independently and collaborates with DV for closure and debug.

Design and implement RTL and system-level SoC modules, perform logic synthesis and timing analysis, integrate modules into SOC, collaborate with architects and verification teams, support silicon bring-up, and improve design flows and methodologies to enhance efficiency and chip yield.

As a Frontend Leaning Full Stack Engineer, you will improve internal software, enhance user-facing tools, and shape UX/UI for founders and investors, focusing on efficiency and product ownership.

Design and implement front-end experiences for internal data-driven web applications: conduct user research, create wireframes and prototypes, build production UI components, write automated UI tests, document designs and implementations, collaborate with data scientists and engineers, and improve usability for clinical and operational workflows.

Support full lifecycle natural gas distribution projects: review public improvement plans, prepare designs and calculations, develop pipeline routes, create construction estimates, coordinate with stakeholders, and perform site visits and field support.

Design and implement full‑custom analog/mixed‑signal layouts for high‑performance IP in advanced FinFET nodes. Translate schematics to manufacturable layouts, optimize floorplans for PPA and matching, run and close physical verification (DRC/LVS/ERC/DFM/antenna), perform post‑layout extraction/simulation, and integrate blocks into SoCs. Develop layout automation and collaborate with circuit designers to meet performance, noise, and reliability targets.

Lead microarchitecture and front-end RTL design for wafer-scale AI chips. Define functional specs, develop RTL, integrate IP, collaborate with PD/DFT/software teams, debug silicon bring-up, and meet PPA goals.

Design and analyze 3D integrated ASIC/SoC products, including packaging, power, clock, cooling, and 3D die-stacking. Perform block and full-chip physical verification (DRC/LVS), IR/EM and SI/PI analysis, optimize power/performance/area, enhance flows with Tcl/Python scripting, and collaborate with RTL and architecture teams on novel 3D integration R&D.

Lead synthesis, placement, routing, and full-chip physical design for high-speed AI silicon. Perform block and full-chip physical verification, timing closure, power/performance/area optimization, DRC/LVS and IR/EM resolution, STA and constraint drafting, floorplanning, and script-based flow enhancements. Collaborate with RTL teams to integrate blocks into the full-chip architecture.

Lead front-end RTL engineer responsible for functional specification, micro-architecture, RTL development, synthesis, and integration. Manage external ASIC vendors, collaborate with PD, verification, DFT, software and system teams, and debug silicon-level functional, timing, and power issues during bring-up to meet PPA and test coverage goals.

Design and analyze 3D integrated ASIC/SoC products, including block and full-chip physical design, verification, packaging, power, clock, and cooling analysis. Collaborate with architecture and RTL teams to optimize power/performance/area, resolve DRC/LVS and IR/EM issues, enhance flows via scripting, and perform R&D on novel 3D integration concepts and full-chip integration.

Develop substation physical design drawings, calculations, and documentation; support site layout, equipment placement, code compliance, cross-disciplinary coordination, quality checks, client meetings, and mentor junior engineers to ensure timely, constructible deliverables.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Simulate and analyze ultra-high-speed PCB channels (112G+ SerDes), provide SI guidance to digital hardware designers, perform TDR/VNA and oscilloscope measurements, document results, and implement signal integrity best practices across cross-functional teams.

Drive Thunderbolt's AI product experience by turning ambiguous concepts into working prototypes and production front-end features. Define interaction patterns for chat, search, agents, automation, and knowledge retrieval; prioritize usability, accessibility, security, and enterprise requirements; build reusable components and design-system elements; collaborate with product, design, and engineering to validate and productionize features.

Lead design-engineering for Thunderbolt by turning ambiguous AI product ideas into prototypes and production-ready front-end experiences. Build prototypes in the codebase, define AI interaction patterns, improve usability/accessibility, create reusable components and design-system elements, and partner with cross-functional teams to ensure enterprise readiness, security, and user trust.

Design building electrical systems, including power and lighting for healthcare projects. Oversee construction administration and coordinate with internal teams.