Top Senior Hardware Engineer Jobs in Portland, OR

Validate server hardware components and new platform designs through power, thermal, performance, firmware, and automation testing. Maintain hardware test infrastructure, document technical findings, coordinate with ODM/OEM partners, and collaborate with software teams on BIOS, kernel, and firmware optimization. The role requires expertise in server architectures, validation methodologies, Linux, Python, Bash, Redfish, IPMI, and industry standards including PCIe, NVMe, and DDR.

Pipeline hiring for hardware engineers at all experience levels. Work includes circuit board design, schematic capture, component selection and prototype bring-up, hardware debug/testing and failure analysis, integration with firmware/software teams, and design for manufacturability with production handoff.

Design and deliver secure compute hardware for post-quantum cryptography and orbital/terrestrial systems. Own power, thermal, enclosure, and bus architecture design; collaborate with software, security, and systems teams; support FPGA integration, manufacturability, reliability, and environment-specific constraints (radiation, vibration, thermal-vacuum). Deliver iterative hardware releases on aggressive timelines.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.

Lead architecture, bring-up, validation, optimization, and deployment of networking infrastructure for large-scale AI training and inference. Define networking requirements, design Layer 3/4 and RDMA/AI fabric solutions, develop validation and observability tooling, perform packet-level debugging and root-cause analysis, and collaborate across silicon, firmware, software, and Azure teams to ensure performance, scalability, and reliability of hyperscale AI clusters.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Provides technical leadership and customer support for Marvell switching, PHY, and processor SoC products. Architects hardware solutions, investigates and reproduces hardware and software issues, performs schematic reviews, debugs boot sequencing and customer-reported problems, and supports Linux BSPs, U-Boot, device drivers, and board designs. Serves as a liaison among customers, Avnet field applications engineers, and Marvell engineering teams, while delivering training and occasional customer-site support.

Design, test, and validate next-generation server hardware and components for performance, power, and reliability. Diagnose and resolve hardware issues across engineering and manufacturing, document results, and develop/maintain test scripts. Collaborate with internal teams and OEM/ODM partners to scale platforms for global deployment.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

Design and optimize high-speed, high-density ASIC package layouts and substrate breakouts. Perform pinout optimization, routing, placement, stack-up, power distribution, CAD library development, feasibility studies, and productivity methodology improvements while collaborating with package leads and cross-functional teams.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.