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YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design high-speed analog mixed-signal circuitry for AI data center products, ensuring performance metrics like power and jitter while managing detailed design processes.
Top Skills: Analog Mixed-Signal DesignClock And Data RecoveryClocking CircuitryCmosEmxMatlabPllPower IntegritySignal IntegritySimulinkVcoVerilogVeriloga
YesterdaySaved
In-Office
San Jose, CA, USA
163K-262K Annually
Expert/Leader
163K-262K Annually
Expert/Leader
Semiconductor
Lead the design and development of high-speed SerDes solutions for AI connectivity. Oversee front-end digital design, verification, and integration processes while ensuring compliance with specifications and methodologies.
Top Skills: Eda IntegrationRtl DesignTsmc
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design high-speed analog mixed-signal circuitry for AI data center products, assess design bugs, and manage design methodologies.
Top Skills: Clock And Data RecoveryClock DistributionCmosEmxMatlabPllSimulinkVcoVerilogVeriloga
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design high-speed analog mixed-signal circuitry for AI data center connectivity products. Requires 8+ years in advanced CMOS design and strong analytical skills.
Top Skills: AdcCmosEmxMatlabPllSimulinkVcoVerilogVeriloga
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The role involves contributing to ASICs for data center products, requiring expertise in physical design, verification, and scripting skills.
Top Skills: CaliberPerlPythonRedhawkShellTclVirtuoso
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design high-speed analog mixed-signal circuitry for AI data center connectivity products, requiring expertise in design methodologies and advanced CMOS technologies.
Top Skills: CdrCmosEmxMatlabPllSimulinkVcoVerilogVeriloga
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design and develop high-speed SerDes RTL circuits, focusing on performance, power, and cost metrics. Collaborate across teams and use various design tools.
Top Skills: LintNcsimNcverilogSimvisionSystem VerilogVerilog-Hdl
YesterdaySaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
As a Senior ASIC Physical Design Engineer, you will work on SerDes connectivity ASICs for data center products, focusing on physical design tasks and methodologies.
Top Skills: AsicCaliberPerlPhysical DesignPythonRedhawkShellTclVirtuoso
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Reposted YesterdaySaved
In-Office
Santa Clara, CA, USA
96K-184K
Entry level
96K-184K
Entry level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Design and implement ASIC floorplans, optimize designs, solve congestion issues, and develop tools for chip area and execution speed.
Top Skills: C/C++CadPerlPythonSystem VerilogVerilog
Reposted YesterdaySaved
In-Office
Cassville, MO, USA
Mid level
Mid level
Energy • Renewable Energy
As a Design Engineer III, you'll optimize products, lead problem-solving efforts, and collaborate with various teams to enhance product development and manufacturing processes.
Top Skills: 3D ModelingCfdDfmaFeaPfma
Reposted YesterdaySaved
In-Office
Emeryville, CA, USA
150K-210K Annually
Entry level
150K-210K Annually
Entry level
Hardware • Robotics
As a Device Development Engineer, you will design, manufacture, and test microscale prototypes in a hands-on role. You'll work collaboratively to innovate solutions for microscale systems, generate CAD documentation, perform experiments, and operate advanced metrology tools.
Reposted YesterdaySaved
In-Office
Mountain View, CA, USA
100K-160K
Senior level
100K-160K
Senior level
Hardware • Software
The role involves performing static timing analysis, debugging timing constraints, and driving timing closure in complex semiconductor products.
Top Skills: FishtailPrimetimePythonSta Tools Like TempusTclTiming Constraint Verification Tools Like TimevisionTweaker
Reposted YesterdaySaved
In-Office
New York, NY, USA
75K-225K
Mid level
75K-225K
Mid level
Design
The Computational Design Engineer will develop computational design processes, conduct research in various computational fields, and collaborate with a multidisciplinary team to realize design concepts and prototypes.
Top Skills: C++23GrasshopperPythonRhinoSidefx HoudiniTouch DesignerUnityUnreal Engine
Reposted YesterdaySaved
In-Office
Fargo, ND, USA
75K-90K Annually
Mid level
75K-90K Annually
Mid level
Information Technology • Consulting
The Mechanical Design Engineer will work on CAD designs for heavy machinery, collaborating with suppliers and ensuring compliance with safety standards.
Top Skills: CadCreo
Reposted YesterdaySaved
In-Office
Santa Clara, CA, USA
155K-250K Annually
Senior level
155K-250K Annually
Senior level
Artificial Intelligence • Machine Learning • Software
Design analog-mixed signal integrated circuits, analyze performance, optimize layouts for low power, and assist in silicon testing and integration.
Top Skills: CadenceSynopsis
Reposted YesterdaySaved
In-Office
San Jose, CA, USA
119K-190K Annually
Senior level
119K-190K Annually
Senior level
Semiconductor
Design and implement high-performance ASIC products by collaborating with various teams, focusing on RTL design, verification, and system requirements.
Top Skills: High Performance Communications Asic,803.3 EthernetVerilog,Vhdl,Perl,Tcl,Unix,Eda Tools,Synopsys Tool Suite,Primetime,Rtl
Reposted YesterdaySaved
In-Office
Mountain View, CA, USA
181K-290K
Senior level
181K-290K
Senior level
Automotive
The Staff Mechanical Design Engineer will design opto-mechanical enclosures, collaborate on production, and analyze sensor performance, contributing to next-gen automotive sensors.
Top Skills: Ansys WorkbenchCatiaMatlabPythonZemax
Reposted 2 Days AgoSaved
In-Office
Seattle, WA, USA
141K-197K Annually
Senior level
141K-197K Annually
Senior level
Aerospace
The role involves designing and developing mechanical systems for space vehicles, supporting integration activities, and ensuring compliance with engineering specifications.
Top Skills: 3D Modeling ToolsAnsysCreo (Pro-E)Nastran
2 Days AgoSaved
In-Office
Santa Clara, CA, USA
147K-220K
Senior level
147K-220K
Senior level
Semiconductor
The Principal Design Engineer will develop micro-architecture for SoCs, collaborate with various teams, debug simulations, and mentor junior engineers.
Top Skills: PerlPythonSystemverilogVerilog
Reposted 2 Days AgoSaved
In-Office
Alameda, CA, USA
Senior level
Senior level
Energy
Engineer will develop NDT solutions, collaborate with teams, mentor junior engineers, and ensure compliance with codes and standards for reactor systems.
Top Skills: Computed TomographyEddy Current MethodsNon Destructive Testing MethodsPhased-Array MethodsPotential Drop MethodsRadiographyUltrasonic Testing
2 Days AgoSaved
In-Office
Maplewood, MN, USA
96K-117K Annually
Senior level
96K-117K Annually
Senior level
Healthtech • Pharmaceutical • Manufacturing
The Design Engineer leads design projects by creating concepts and specifications, analyzing problems, and ensuring project timelines and costs are met, while also preparing technical documentation and supporting team development.
Top Skills: CadEmatrix PlmEnoviaNxSolidworksUnigraphics
2 Days AgoSaved
In-Office
Santa Clara, CA, USA
166K-268K Annually
Expert/Leader
166K-268K Annually
Expert/Leader
Cybersecurity
The Senior Principal ASIC Design Engineer will lead complex ASIC designs, mentor engineers, guarantee design and micro-architecture specifications, and drive major design projects.
Top Skills: BashCC++PerlPythonSilicon ValidationSystemverilog
2 Days AgoSaved
Remote
USA
100K-100K
Senior level
100K-100K
Senior level
Logistics • Transportation
The Solutions Design Engineer II develops and designs supply chain solutions, calculates operational requirements, supports bid submissions, optimizes logistics networks, and engages with customers to deliver compelling proposals.
Top Skills: AutomationCadJdaLlamasoftMheMicrosoft Office SuiteOtmTableauVisibility Tools
2 Days AgoSaved
In-Office
Westborough, MA, USA
100K-149K
Mid level
100K-149K
Mid level
Semiconductor
As a Senior Physical Design Engineer, you'll execute physical design tasks, develop methodologies, and collaborate across teams to ensure successful chip designs.
Top Skills: Eda ToolsPerlPythonTclVerilogVhdl
2 Days AgoSaved
In-Office
Burlington, VT, USA
126K-186K
Senior level
126K-186K
Senior level
Semiconductor
As a Senior Staff Physical Design Engineer, you'll lead physical design efforts, perform synthesis, routing, and collaborate on timing analysis, driving improvements in chip design processes.
Top Skills: Cadence InnovusPerlPythonSynopsys Fusion CompilerTclVerilogVhdl
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