Top Design Engineer Jobs

The Senior Physical Design Engineer at NVIDIA will be responsible for the physical design and implementation of GPUs and ASICs across various markets. Key tasks involve establishing design methodologies, floorplanning, power/clock distribution, timing closure, static timing analysis, and physical verification, leveraging extensive experience in VLSI physical design on advanced technologies.

As a System Design Engineer, you will develop GPU and Tegra hardware products, collaborate with teams on cost and performance optimizations, lead debugging efforts, create schematics, supervise PCB layouts, and improve design flows while ensuring product documentation for manufacturing.

The Senior ASIC Physical Design Engineer will focus on the physical design of high-frequency, low-power CPUs and GPUs, handling netlist-related tasks like equivalence checking, asynchronous checking, logic synthesis, and timing convergence management. This role requires expertise in using industry-standard EDA tools and proficiency in scripting languages.

Develop and implement high-speed interfaces and analog circuits at data rates of 25Gbps and higher. Responsibilities include schematic design of deep-submicron CMOS technologies, transistor design, circuit verification, and optimization for system performance while collaborating with layout engineers and supporting post-silicon debugging.

As a Senior ASIC Physical Design Engineer at NVIDIA, you will lead physical design for high-performance CPUs and GPUs, focusing on optimizing PPA. Responsibilities include floor planning, synthesis, implementation, and timing closure, collaborating across teams to solve complex design challenges.

The role involves automating hardware testing, building user-friendly interfaces for complex hardware tasks, and developing data visualization tools. The engineer will also be responsible for managing compute farms, optimizing data handling, and debugging testing scripts in Python and JavaScript.

This role involves designing and implementing high-performance, low power CPU subsystems. Responsibilities include driving micro-architecture development, implementing in RTL, optimizing for performance, and collaborating with verification and physical design teams. The candidate will also support hardware engineering activities and develop tools related to design processes.

The Senior Mask Layout Design Engineer at NVIDIA will perform physical layout for mixed-signal functions using Cadence tools and engage in floor planning and verification. They will collaborate with ASIC and mixed-signal engineers for VLSI product integration, leveraging their expertise in sub-micron CMOS technologies and layout concepts.