Top Design Engineer Jobs

Design and validate aircraft structural and interior payload systems for legacy platforms. Review supplier design changes for compliance, execute design releases, coordinate cross-functional engineering, lead projects, mentor junior engineers, and improve analytical processes using industry CAD/PDM tools.

Seeking a Senior Design Engineer for Mechanical Flight Controls, overseeing design solutions, compliance, and troubleshooting for aerospace projects.

Lead mechanical design, simulation, analysis and testing of rotating and static turbomachinery components (rotors, stators, blisks, disks, impellers). Perform FEA (modal, vibration, deflection, crack growth, burst, fatigue, thermal, stack), test execution and data analysis, generate engineering documentation, lead design reviews, mentor junior engineers, drive process/tool improvements, and support proposals for commercial and military customers.

Design and build end-to-end web and mobile experiences: lead research, concepts, and prototypes; create and maintain design systems; implement responsive, accessible front-end features and back-end APIs; partner with product and data teams to optimize performance, accessibility, and security; shape engineering and design standards.

The Senior Package Design Engineer will design and optimize semiconductor packages, collaborating with cross-functional teams to enhance performance and manufacturability, while leading layout activities and contributing to standards and guidelines.

Design and implement engineering solutions for electronic components, ensuring compliance with engineering principles and collaborating with stakeholders throughout development cycles.

Lead design and validation of rugged electronics packaging for defense systems. Perform thermal, vibration, and stress analysis; oversee prototyping, testing, documentation, and compliance with military standards. Mentor junior engineers, coordinate cross-functional integration, manage project planning, risks, schedules, and export-control documentation.

The role involves designing SoC architecture and integration, optimizing memory subsystems, and collaborating on pre/post-silicon validation processes.

Build and scale cell characterization infrastructure for standard and custom cells across process nodes. Develop automated MCMM flows, Liberty model generation and validation, integrate flows with design/verification/CAD teams, root-cause SPICE/STA/silicon mismatches, and enable characterization for HBM, DRAM, TSV, and high-speed interfaces.

This role involves designing and optimizing RTL for DRAM digital circuits, performing STA, collaborating across teams, and ensuring robust designs.

Contribute to NAND datapath design and layout: manage IO/datapath blocks, model parasitics, optimize area/power, collaborate on specs, drive silicon experiments and debug, and document results. Leverage AI/automation to accelerate workflows.

Design and optimize DRAM memory circuits from gate-level to full-chip, lead schematic block development, run advanced SPICE/Verilog simulations, drive power/speed/area tradeoffs, and collaborate cross-functionally on design rules, device requirements, and silicon validation.

Design and implement RTL for HBM SoC logic die, integrate internal and third-party IP, support SoC-level integration (clocking, reset, power intent), assist pre-/post-silicon validation and bring-up, and collaborate cross-functionally to meet performance, power, area, and manufacturability targets.

Lead end-to-end DRAM circuit design and optimization across memory array, control logic, datapath, and test logic. Perform SPICE and Verilog simulations, incorporate layout parasitics, evaluate power/performance/area trade-offs, define validation/test-chip strategies, and collaborate with cross-functional teams to enable manufacturable, high-performance DRAM products.

As a Staff Design Engineer at Micron, you'll design and analyze digital and analog circuits for DRAM products, ensuring manufacturability and performance through collaboration and hands-on optimization.

Design and implement SystemVerilog RTL and microarchitectures for AI-optimized memory systems; perform synthesis and PPA analysis; document microarchitecture; evaluate tradeoffs and drive implementations from specification through silicon.

Design and validate analog/digital circuits for memory products (HBM/DRAM). Perform schematic entry, layout, parasitic modeling, SPICE simulations, timing/area/power trade-off analysis, and collaborate across product, test, process, and CAD teams to ensure manufacturability and tape-out readiness.

Lead development, layout, and optimization of high-speed datapath IO circuits for next‑gen NAND flash, driving AI-first workflows. Own architecture decisions, verify major IO blocks, redesign engineering workflows to embed AI, mentor teams, and collaborate across functions to meet aggressive data-rate and power targets.

Design and optimize NAND flash array circuits and waveforms; perform schematic, block-level, subsystem and full-chip simulations; lead layout implementation and parasitic extraction; collaborate with firmware, analog, validation, and manufacturing teams; develop Python automation and AI-assisted EDA utilities; evaluate die size, power, and reliability tradeoffs and produce documentation.

Design and simulate mixed-signal and PHY-adjacent circuit blocks for HBM, develop behavioral models (Verilog-A/AMS or SystemVerilog), run SPICE and mixed-signal simulations, support parasitic modeling and validation, collaborate on integration and silicon bring-up.

Implement SoC physical design from netlist to GDSII: floor-planning, placement, CTS, routing, and optimization to meet PPA. Drive MMMC timing closure, integrate complex IP, perform physical signoff (DRC/LVS/IR/EM/timing), support tape-out and post-silicon debug, collaborate across RTL/DFT/packaging/manufacturing, and improve flows via scripting and AI-enabled tools.

As a Principal Design Engineer, you'll architect high-performance DRAM circuits, collaborate with teams, perform advanced circuit simulations, and manage layout resources to optimize memory technologies.

Design and implement embedded control and diagnostic algorithms for vehicle brake and electrification systems using model-based and hand code (C/C++/MATLAB/Simulink). Define calibration strategies, tests (MIL/SIL/HIL/CPUU), and interfaces; perform modeling, simulation, data analysis, root-cause support, and integration. Mentor team members, build tools and training, and collaborate across teams. Hybrid role with minimal travel.

The Design Engineer designs and analyzes digital and analog circuits for memory products, collaborates with various teams, and validates designs throughout the product lifecycle.

Design and analyze digital and analog memory circuits (arrays, control logic, datapaths, decoders) using simulation and layout tools. Optimize power, speed, die size, manufacturability, and apply AI-enabled tools to improve design flow while collaborating with cross-functional teams for validation and product readiness.