Top Design Engineer Jobs

Design Engineer will rapidly prototype and iterate mobile products (primarily iOS), build tooling and internal systems, collaborate with designers, PMs, and engineers to drive product strategy, test with researchers, and ship polished experiences to hundreds of millions of users. Role involves presenting work to leadership and occasionally prototyping on web, AR, and AI platforms.

Design and deliver FPGA systems across the development lifecycle: architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab bring-up and debug, product support, and FPGA security. Mentor engineers, collaborate on cross-functional teams, and develop testbenches and scripts to support verification and lab testing.

Design, integrate, and verify electrical test stands for complex digital, analog, RF, and optical modules. Develop circuits, interconnects, environmental controls, and test procedures; lead and mentor junior engineers; interface with manufacturing, quality, suppliers, and customers; drive root-cause resolution and continuous improvements to increase yield and throughput.

Lead end-to-end infrastructure integration across networking, cloud, IAM, collaboration, and security. Create integration roadmaps, apply SRE and IaC practices, define cloud hosting strategy, implement IAM (SSO/MFA/PAM), guide migrations, ensure compliance and operational resilience, and align solutions with enterprise architecture standards.

Lead architecture, design, and verification of mixed-signal avionics hardware and FPGA/ASIC RTL for flight-critical systems. Own full product lifecycle from requirements, schematic and PCB work through FPGA implementation, timing closure, verification, qualification, and production release. Support avionics integration, testing, reliability analyses, and ground test support.

Design, layout, simulate, and optimize DRAM memory circuits focusing on performance, power, area, and manufacturability. Develop schematics for arrays, control logic, decoders, datapaths, and test circuitry, validate designs via SPICE/Verilog simulations, integrate parasitics, and support test chip development and silicon validation with AI-enabled improvements.

Design and optimize next-generation memory products. Responsibilities include circuit design, layout management, verification, and cross-functional collaboration for manufacturability.

Lead silicon debug and product quality for HBM products, influencing design decisions and ensuring system stability across customer platforms. Drive continuous improvement through technical leadership and cross-functional collaboration.

The Staff Design Engineer is responsible for designing and verifying digital circuits for memory products, collaborating with teams, and ensuring high performance and quality standards.

As a Member of Technical Staff, design and implement high-performance memory solutions for AI, focusing on microarchitecture, performance, power, and reliability.

Lead architecture and delivery of high-performance DRAM circuits and subsystems. Optimize floorplans, routing, power delivery, and timings; perform advanced simulations (FINESIM, HSPICE, Verilog); model parasitics and verify signal/power integrity; drive simulation-to-silicon correlation, layout decisions, tape-out support, and cross-functional technical coordination and reviews.

Define and implement DFT and testmode requirements for memory products. Design and evaluate DFT circuits and architectures, validate via modeling and simulation, influence early design planning, and collaborate with design, verification, and manufacturing teams to improve test coverage, scalability, and manufacturability.

Lead datapath design for NAND flash memory, focusing on TSV interface and wide parallel data buses. Drive architecture decisions, timing and signal/power integrity analysis, DFT and Verilog-based verification, post-silicon validation, and multi-team coordination to meet performance, power, and reliability goals.

The SoC Physical Design Engineer will manage SoC block implementations, ensure timing closure, integrate IPs, and conduct physical signoff while driving design optimization.

Lead end-to-end physical design for HBM base and memory dies, including floorplanning, placement, CTS, routing, power integrity, timing and signoff. Drive HBM-specific architecture, PDN/thermal/IR/EM closure, packaging integration, ECO strategies, automation, and mentor engineers to improve flows across HBM generations.

Design and integrate SoC subsystems (PCIe, DDR/LPDDR, HBM, UCIe, Ethernet); author micro-architecture specs; develop RTL in Verilog; perform static checks (CDC, RDC, X-Propagation, linting); collaborate with verification, performance analysis, and backend teams for floorplanning and timing closure; improve design methodologies and mentor team members while supporting project management.

The Staff Design Engineer will debug silicon issues, collaborate cross-functionally, support design updates, and improve product quality for HBM products.

Drive SoC physical implementation from netlist to GDSII including floorplanning, placement, CTS, routing, timing closure (MMMC), power integrity, and physical signoff. Integrate complex IP, partner with DFT/packaging/manufacturing, support tape-out and post-silicon debug, and improve flows via scripting and automation.

Design and analyze digital and analog circuits for HBM base and DRAM core dies. Develop schematic blocks, run circuit simulations (SPICE/Verilog), lead floor-planning and layout extraction, validate reliability, support tape-outs, and collaborate across design, test, process, and product teams to optimize performance, cost, quality, and manufacturability.

Lead analysis of current and next-generation DRAM/DDR memory technologies across electrical, thermal, power, and performance domains. Identify performance gaps, evaluate tradeoffs, and provide design guidance to architecture, firmware, validation, and product teams. Drive multi-functional alignment, deliver technical recommendations, and use AI tools to model design gaps and summarize data for strategy and decision-making.

Design and optimize digital and analog circuits for DRAM memory products. Perform circuit design, layout, simulation, verification, parasitic extraction, and silicon validation. Collaborate cross-functionally to meet power, performance, area, manufacturability, and reliability goals while applying AI-enabled tools to improve design workflows.

Design, optimize, and verify analog and mixed-signal block-level circuits for DRAM. Propose new circuit topologies, expand verification and yield robustness, supervise analog layout and post-layout simulation, support silicon-to-simulation correlation, and collaborate with global teams and EDA/data science partners to leverage AI-assisted design flows.

As a Senior Design Engineer, you will design, analyze, and validate analog and mixed-signal circuits for memory products, optimize performance, and collaborate with cross-functional teams to develop innovative solutions.

Design, optimize, and verify analog and mixed-signal block-level circuits for DRAM. Improve circuit topologies, expand verification for yield, support post-layout simulation and silicon correlation, and apply AI/automation to boost design efficiency.

Design and verify digital circuits for NAND memory products. Develop RTL and schematics, perform gate-level and post-layout simulations, support netlist bring-up, collaborate on validation and silicon bring-up, and apply AI tools to streamline design tasks.