Top Design Engineer Jobs

Reposted 12 Days AgoSaved
In-Office
Santa Clara, CA, USA
100K-137K Annually
Mid level
100K-137K Annually
Mid level
Artificial Intelligence • Semiconductor • Manufacturing
As a Mechanical Engineer, you'll resolve mechanical issues, design tooling, coordinate component procurement, and ensure compliance with industry standards in manufacturing processes.
Top Skills: Cad SoftwareFlow AnalysisGd&TManufacturing MethodsMaterial SelectionSheet Metal DesignThermodynamics
Reposted 12 Days AgoSaved
In-Office
San Jose, CA, USA
160K-195K Annually
Senior level
160K-195K Annually
Senior level
Big Data • Information Technology
The Senior Digital Design Engineer will design and implement digital designs for high-performance connectivity solutions, collaborating across teams for successful product delivery.
Top Skills: AsicCadenceCmosDdrEthernetPciePythonSynopsysSystemverilogUvm
Reposted 12 Days AgoSaved
In-Office
San Jose, CA, USA
430K-430K Annually
Senior level
430K-430K Annually
Senior level
Big Data • Information Technology
The Principal Digital Design Engineer will architect and implement complex digital designs for connectivity solutions, oversee micro-architecture and RTL implementation, and mentor junior engineers.
Top Skills: CadenceCxlEthernetNvlinkPcieSynopsysUalinkUvm
Reposted 12 Days AgoSaved
Hybrid
Austin, TX, USA
Expert/Leader
Expert/Leader
Hardware • Software
Lead digital IC design for mixed-signal CMOS devices from concept to production. Design and validate digital and DSP IP, model control loops in Matlab/Simulink, convert subsystems into silicon-ready designs, perform lab debug and post-silicon validation, characterization, and production test, and support integration with SoC architectures.
Top Skills: ArmCmosMatlabPlace And RoutePteRisc-VSimulinkSynthesisTiming AnalysisVerilog
Reposted 12 Days AgoSaved
Hybrid
Austin, TX, USA
Expert/Leader
Expert/Leader
Hardware • Software
Manage and grow the IP Integration Digital team; define strategy, requirements, and schedules. Oversee transistor-level design, characterization, Verilog modeling, and Cadence-based simulation/layout of custom and 3rd-party IP. Collaborate with product, foundry, layout, and quality teams to deliver qualified IP for mixed-signal chips.
Top Skills: CadenceIbisLayoutTransistor-Level SimulationVerilog
12 Days AgoSaved
In-Office
3 Locations
111K-169K Annually
Senior level
111K-169K Annually
Senior level
Aerospace
The Mechanical Design Engineer III will lead the design and development of cryogenic pumps for lunar applications, collaborating with experts and managing pump life cycles.
Top Skills: Cad (Creo)Plm (Windchill)
Reposted 12 Days AgoSaved
In-Office
San Francisco, CA, USA
Senior level
Senior level
Artificial Intelligence • Software • Energy • Renewable Energy
Design isolated and non-isolated converter stages, implement advanced topologies, perform trade-off analysis, develop control algorithms, and coordinate with design and manufacturing teams for power electronics systems.
Top Skills: GanPcbaPower ElectronicsSic
Reposted 12 Days AgoSaved
In-Office
Sunnyvale, CA, USA
Mid level
Mid level
AdTech • Computer Vision • Machine Learning • Software
Design cost-effective controllers for cellular modems, focusing on CPU subsystem development and micro-architecture for 5G applications.
Top Skills: ArmClock TreeLow Power DesignMipsRisc Cpu ArchitectureRisc-VRtl IntegrationSimulationSta
Reposted 12 Days AgoSaved
In-Office
Sunnyvale, CA, USA
Senior level
Senior level
AdTech • Computer Vision • Machine Learning • Software
Design and implement features in RISC-V CPU cores, perform verification, collaborate on design optimization, and ensure high-quality delivery.
Top Skills: ChiselRisc-VScalaSystem VerilogVerilogVhdl
Reposted 12 Days AgoSaved
In-Office
San Francisco, CA, USA
175K-300K Annually
Mid level
175K-300K Annually
Mid level
Software
As the first Design Engineer at Serval, you will collaborate closely with product and engineering teams to create high-quality, production-ready software using React and TypeScript while maintaining design fidelity.
Top Skills: AWSCSSFigmaFramer MotionGoKubernetesPostgresReactTemporalTypescript
Reposted 12 Days AgoSaved
In-Office
2 Locations
151K-261K Annually
Mid level
151K-261K Annually
Mid level
Biotech
Design and implement micro-architecture and RTL for low-power DSPs and hardware accelerators, optimize hardware/software interfaces, model and profile energy/performance trade-offs, collaborate on silicon bring-up and verification, and develop emulation models and test environments.
Top Skills: CC++DspEmulationHardware AcceleratorsmacOSPhyPythonRtlRustSocSystemcSystemverilog
Reposted 12 Days AgoSaved
In-Office
2 Locations
116K-234K Annually
Senior level
116K-234K Annually
Senior level
Biotech
The Digital IC Design Engineer will develop micro-architecture and RTL for low-power processors and hardware accelerators in brain-computer interfaces, collaborating with teams on optimization and testing.
Top Skills: C/C++PythonSystemverilog
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Reposted 12 Days AgoSaved
In-Office
Austin, TX, USA
102K-244K Annually
Senior level
102K-244K Annually
Senior level
Biotech
The Senior Mechanical Design Engineer will design HVAC, plumbing, and process utility systems for various facilities, ensuring code compliance and integration with manufacturing processes.
Top Skills: AutocadBluebeamCarrier HapComcheckMicrosoft ProductsNavisworksRevit MepTrane Trace
Reposted 12 Days AgoSaved
In-Office
4 Locations
122K-232K Annually
Mid level
122K-232K Annually
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
The Physical Design Engineer will focus on physical design aspects, including floor-planning, synthesis, timing closure, and generating scripts to optimize design tools for neuromorphic computing projects.
Top Skills: C++Fusion CompilerJavaPerlPrimetimePythonSynopsys ToolsTclVcs
Reposted 12 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Artificial Intelligence • Information Technology • Software • Database • Generative AI
The RTL/PD Engineer handles RTL-to-PD handoffs, timing closure, floorplanning, and creates automated design flows, collaborating with various teams for seamless integration and quality checks.
Top Skills: Ai ToolsCadence ToolsPdRtlSynopsys ToolsSystemverilogVerilog
Reposted 12 Days AgoSaved
In-Office
Phoenix, AZ, USA
164K-232K Annually
Senior level
164K-232K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
The role involves developing CPU logic architecture, optimizing designs, resolving RTL issues, and collaborating on microarchitecture features for performance and efficiency.
Top Skills: Cpu DesignMicroarchitecturePower And Performance AnalysisRtl Coding
Reposted 12 Days AgoSaved
Remote
United States
180K-260K Annually
Senior level
180K-260K Annually
Senior level
Defense • Manufacturing
The engineer will define and implement ASIC package architecture, focusing on FC-BGA and MCM solutions, collaborating on package design and ensuring successful production of high-performance ASICs.
Top Skills: AdsAsic DesignFc-BgaHfssMcmSi Wave
Reposted 12 Days AgoSaved
In-Office
Los Angeles, CA, USA
140K-175K Annually
Senior level
140K-175K Annually
Senior level
Defense • Manufacturing
The role involves mechanical design and analysis for a high-powered electric propulsion system, managing vendors, testing hardware, and validating designs through production and flight.
Top Skills: CadFeaGd&T
Reposted 12 Days AgoSaved
Remote
United States
200K-280K Annually
Senior level
200K-280K Annually
Senior level
Defense • Manufacturing
The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.
Top Skills: AdsFc-BgaHfssMcmSiwave
Reposted 12 Days AgoSaved
In-Office
York, NY, USA
86K-99K Annually
Entry level
86K-99K Annually
Entry level
Professional Services
The Design Engineering Specialist will assist in hydrologic and hydraulic analysis and design stormwater management systems and pipe conveyance systems.
Top Skills: Hec-RasSwmmTr-55
Reposted 12 Days AgoSaved
In-Office
Hooksett, NH, USA
Senior level
Senior level
Design • Manufacturing
The Electrical Design Engineer will design power and low-voltage systems, create Revit drawings, coordinate with teams, and review site documents.
Top Skills: Revit
Reposted 12 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Mobile
The role involves designing and simulating RF power amplifiers, with a focus on innovation in CMOS SOI technology for Wi-Fi 7 systems.
Top Skills: CadenceEmxHfssMatlabMomentumPythonRfpro
Reposted 12 Days AgoSaved
In-Office
Los Angeles, CA, USA
125K-195K Annually
Senior level
125K-195K Annually
Senior level
Software
The Senior FPGA Design Engineer collaborates on designing signal processing algorithms for MIMO wireless systems and supports FPGA-based system development.
Top Skills: FpgaMatlabRtlVivadoXilinx
Reposted 12 Days AgoSaved
In-Office
Burlington, VT, USA
Senior level
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves static timing analysis, integrating designs, and providing mentoring, while working with teams to ensure design convergence using EDA tools.
Top Skills: Cadence InnovusEda ToolsPrimetimePythonShellTclVerilog
Reposted 12 Days AgoSaved
In-Office
Irvine, CA, USA
165K-250K Annually
Senior level
165K-250K Annually
Senior level
Software
The Principal FPGA/RTL Design Engineer will design and implement signal processing algorithms for wireless networking, collaborating with teams on system engineering, RTL coding, FPGA synthesis, and hardware verification.
Top Skills: FpgaMatlabPerlPythonSystem-VerilogVerilogVivado IdeXilinx
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