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Top Design Engineer Jobs

Reposted 14 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
150K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software
Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.
Top Skills: Hbm3PythonSystem VerilogVerilator
Reposted 14 Days AgoSaved
In-Office
Santa Clara, CA, USA
7-12
Senior level
7-12
Senior level
Artificial Intelligence • Machine Learning • Software
The Design Verification Engineer will lead SoC verification cycles, utilizing methodologies like UVM/OVM, and contributing to innovative AI architectures.
Top Skills: CC++OvmSystemcSystemverilogUvm
Reposted 14 Days AgoSaved
In-Office
Westborough, MA, USA
140K-207K
Mid level
140K-207K
Mid level
Semiconductor
The Sr. Staff Design Verification Engineer will develop verification plans, create testbenches, perform verification, and collaborate with design teams to resolve issues.
Top Skills: PerlPythonSystem VerilogTclUvmVcs
Reposted 14 Days AgoSaved
In-Office
Westborough, MA, USA
100K-149K
Senior level
100K-149K
Senior level
Semiconductor
The Senior Design Verification Engineer will verify circuitry for chips, focusing on functional testing in an embedded Linux environment, developing drivers and test code, and collaborating with hardware designers.
Top Skills: C/C++LinuxPython
Reposted 14 Days AgoSaved
In-Office
San Carlos, CA, USA
139K-175K Annually
Senior level
139K-175K Annually
Senior level
Healthtech • Manufacturing
The Staff Design Assurance Quality Engineer will provide guidance for product development, ensuring compliance with design requirements, performing risk management activities, and collaborating with various teams to uphold regulatory standards in a fast-paced environment.
Top Skills: Eplm/EqmsGoogle SuiteJamaJIRAMS Office
Reposted 14 Days AgoSaved
In-Office
Los Angeles, CA, USA
100K-145K Annually
Mid level
100K-145K Annually
Mid level
Consulting
The Engineer will perform structural design analysis for transportation structures, manage project coordination, and provide guidance to junior engineers.
Top Skills: Engineering Design SoftwareStructural Modeling Software
Reposted 14 Days AgoSaved
In-Office
2 Locations
100K-500K
Senior level
100K-500K
Senior level
Hardware • Manufacturing
The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.
Top Skills: AtpgJtagSynopsys VcsSystemverilogUvmVerdiVerilog
Reposted 14 Days AgoSaved
Remote
United States
100K-500K
Senior level
100K-500K
Senior level
Hardware • Manufacturing
As a Design Verification Engineer, you will develop verification strategies, execute tests, and mentor juniors while ensuring digital design quality and reliability.
Top Skills: C/C++PerlPythonSystemverilogUvm
Reposted 15 Days AgoSaved
In-Office
Wilmington, MA, USA
109K-150K Annually
Mid level
109K-150K Annually
Mid level
Semiconductor
The Design Verification Engineer will perform system level verification, develop test environments, collaborate with teams, and analyze simulation results.
Top Skills: BashCadence VirtuosoOopPerlPythonSpiceSystem VerilogTclUvmVerilog
Reposted 15 Days AgoSaved
Remote
United States
140K-165K Annually
Senior level
140K-165K Annually
Senior level
Cloud • Information Technology • Database • Energy • Design
The Senior Controls Engineer oversees data center control systems from design to deployment and maintenance, ensuring operational efficiency and compliance.
Top Skills: BacnetBim/RevitBuilding Management SystemsElectrical Power Monitoring SystemsExcelMicrosoft WordModbusMqttOpcPlc ProgrammingProcoreProjectSalesforceSharepointSQL
Reposted 15 Days AgoSaved
In-Office
2 Locations
100K-500K
Mid level
100K-500K
Mid level
Hardware • Manufacturing
The role involves applying formal methods for SoC verification, developing strategies, property libraries, and mentoring junior engineers.
Top Skills: JaspergoldVc Formal
Reposted 16 Days AgoSaved
In-Office
San Jose, CA, USA
157K-243K Annually
Senior level
157K-243K Annually
Senior level
Semiconductor
Design and optimize circuits for high-speed interconnect (Serdes), oversee floor planning and layout, and contribute to silicon validation.
Top Skills: CadenceEmxMatlabPythonSpectreTotem
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Reposted 16 Days AgoSaved
In-Office or Remote
Cambridge, MA, USA
Junior
Junior
Software • Virtual Reality • PropTech
The VR/AR Software Engineer will develop software for multi-user collaborative learning, improve codebase, design interactions, and gather user feedback. Responsibilities include teamwork, client interaction, and possibly leading a small team.
Top Skills: AndroidArC#C++Cloud EngineeringCompute ShadersiOSUnityVisual ShadersVr
Reposted 16 Days AgoSaved
In-Office or Remote
3 Locations
100K-500K
Senior level
100K-500K
Senior level
Hardware • Manufacturing
Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.
Top Skills: PerlPythonRedhawkShellTclVoltus
Reposted 16 Days AgoSaved
In-Office
San Jose, CA, USA
108K-135K Annually
Mid level
108K-135K Annually
Mid level
Healthtech • Manufacturing
The role involves providing quality engineering guidance during product development, ensuring compliance with regulations, and collaborating on design improvements and risk management.
Top Skills: Design For ManufacturabilityEplmEqmsGoogle SuiteJamaMS OfficeStatistical Analysis
Reposted 16 Days AgoSaved
In-Office
Austin, TX, USA
108K-213K
Entry level
108K-213K
Entry level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
As an ASIC Design Verification Engineer at NVIDIA, you'll verify designs, create verification environments, and collaborate with teams to improve efficiency and quality in IP design.
Top Skills: PythonSystem VerilogUvmVcsVerdiVerilog
Reposted 16 Days AgoSaved
In-Office
2 Locations
119K-175K
Mid level
119K-175K
Mid level
Semiconductor
Develop and execute verification plans for subsystems, create and maintain testbenches, debug design issues, and collaborate with teams to ensure coverage.
Top Skills: DdrEthernetPciePerlPythonSystemverilogTclUecUvmVcs
Reposted 16 Days AgoSaved
In-Office
Santa Clara, CA, USA
147K-220K
Senior level
147K-220K
Senior level
Semiconductor
Lead physical design and methodology for high-performance processor chips, enhance EDA tools, and resolve timing issues collaborating with teams.
Top Skills: Eda ToolsPerlPythonTclVerilogVhdl
17 Days AgoSaved
In-Office
San Jose, CA, USA
157K-243K Annually
Expert/Leader
157K-243K Annually
Expert/Leader
Semiconductor
Develop AI models for circuit design, perform circuit simulations, run optimization algorithms, and collaborate on projects at Samsung Display Lab.
Top Skills: Spice,Spectre,Hspice,Cadence Virtuoso,Ade,Python,Pytorch,Tensorflow,Scikit-Learn,Numpy,Pandas
Reposted 17 Days AgoSaved
In-Office
2 Locations
210K-256K Annually
Senior level
210K-256K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software • Semiconductor
Design, layout, and test photonic devices while collaborating with various teams to integrate and validate products in high-volume manufacturing.
Top Skills: Ansys FdtdPhoton DesignPythonSilicon PhotonicsTidy3D
18 Days AgoSaved
In-Office
Goleta, CA, USA
75K-95K
Junior
75K-95K
Junior
Semiconductor • Manufacturing
The Mask Design Junior Engineer will support photolithography processes, design photomasks, ensure compliance, manage tape-out processes, and contribute to yield improvement in a dynamic environment.
Top Skills: KlayoutL-Edit Layout SoftwareSolidworks
18 Days AgoSaved
In-Office
Menlo Park, CA, USA
126K-145K Annually
Senior level
126K-145K Annually
Senior level
Energy
The Senior Mechanical Engineer will lead the design and alignment of critical components for Mainspring's Linear Generator, collaborating across teams and improving engineering processes.
Top Skills: AnsysCadCfdFeaGd&TPdmSolidworks
18 Days AgoSaved
In-Office
Lewisville, TX, USA
Mid level
Mid level
Healthtech • Other • Biotech
The Design Engineer Assurance supports product development and ensures compliance with standards and regulations while collaborating with teams on quality practices and risk management.
Top Skills: CadElectrical EngineeringIec 62304Mechanical Engineering
18 Days AgoSaved
In-Office
2 Locations
122K-184K Annually
Senior level
122K-184K Annually
Senior level
Healthtech
Lead and develop EDA environments and methodologies for advanced packaging technologies, provide design tool support, mentor engineers, and ensure productivity improvements.
Top Skills: Cadence ToolsElectrical Design AutomationLinuxSystemverilogVerilog AmsWindows
Reposted 18 Days AgoSaved
In-Office
Plano, TX, USA
130K-150K Annually
Senior level
130K-150K Annually
Senior level
Other
The Senior FPGA Engineer will design, implement, and optimize FPGA solutions, lead projects, mentor junior engineers, and manage project timelines.
Top Skills: AlteraBashCFpgaPythonQuestasimSystemverilogVerilogVhdlXilinx
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