Top Design Engineer Jobs

Reposted 3 Months AgoSaved
In-Office
Kohler, WI, USA
83K-105K Annually
Mid level
83K-105K Annually
Mid level
Energy • Renewable Energy
The Switchgear Design Project Engineer creates and maintains technical drawings for switchgear systems, collaborates with engineers, and ensures compliance with industry standards while troubleshooting design issues.
Top Skills: AutocadCadCreoPromiseSee Electrical
Reposted 3 Months AgoSaved
In-Office
Redmond, WA, USA
Mid level
Mid level
Information Technology • Internet of Things • Software • Consulting
The Design Verification Engineer will conduct design verification for consumer devices, create automated tests, execute test plans, identify design risks, and communicate project updates.
Top Skills: C++LuaTeam Foundation Server (Tfs)
Reposted 3 Months AgoSaved
In-Office
Boston, MA, USA
217K-267K Annually
Senior level
217K-267K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Lead STA sign-off and timing closure for silicon-photonics ASICs across process nodes. Develop timing constraints, run full-chip STA, automate ECOs with Tempus/PrimeTime, collaborate with RTL/DFT/architecture teams, and document best practices for synthesis through PnR and tapeout signoff.
Top Skills: Asic StaCadenceCmosDftPerlPlace And Route (Pnr)PrimetimePythonRtlShellSilicon PhotonicsSynopsysTclTempusTiming Constraints
Reposted 3 Months AgoSaved
In-Office
Poughkeepsie, NY, USA
83K-196K Annually
Entry level
83K-196K Annually
Entry level
Energy • Utilities
The Engineer - Electric Substation Design is responsible for managing design work and project construction for electric substations, ensuring safety and compliance with corporate procedures while working collaboratively with teams.
Top Skills: Electric SubstationsEngineeringProject Management
Reposted 3 Months AgoSaved
In-Office
Mountain View, CA, USA
175K-215K Annually
Mid level
175K-215K Annually
Mid level
Automotive
Design and execute comprehensive verification plans for custom silicon, developing UVM/SystemVerilog testbenches, reference models, and stimulus. Build scalable automation in Python, integrate VIP, define coverage metrics, debug RTL/testbench/software interactions, and drive verification best practices across teams.
Top Skills: C++Constrained-Random GenerationDdr5EthernetFormal VerificationFunctional CoverageGenerative Ai/LlmsHbmNoc (Network-On-Chip)Pcie Gen5Pcie Gen6PythonRtlSva (Systemverilog Assertions)SystemverilogTestbench DevelopmentUpf (Power-Aware Verification)UvmVerification Ip (Vip)
Reposted 3 Months AgoSaved
Hybrid
Chandler, AZ, USA
Senior level
Senior level
Hardware • Software
Lead functional verification for mixed-signal ASICs including verification planning, UVM testbench development, constraint-random and directed tests, coverage and failure analysis, digital/mixed-signal modeling, gate simulations, and regression/debug infrastructure.
Top Skills: AvmGate-Level SimulationMixed-Signal ModelingOvmSystemverilogTestbench DevelopmentUvmVeraVerilogVerilog AssertionsVhdl
4 Months AgoSaved
In-Office
Los Angeles, CA, USA
180K-225K Annually
Senior level
180K-225K Annually
Senior level
Marketing Tech
Lead end-to-end mechanical design for electromechanical production systems: translate requirements into manufacturable designs, perform FEA and hand calculations, prototype and validate, create drawings/BOMs, apply DFM/DFA, and mentor junior engineers while collaborating with electrical, controls, manufacturing, and suppliers.
Top Skills: Additive ManufacturingCadCnc MachiningFeaLaser CuttingSheet Metal DesignWaterjet
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