Top Design Engineer Jobs

Lead end-to-end verification for chassis and interconnect IPs, build scalable UVM/SystemVerilog testbenches, drive simulation/formal convergence and coverage closure, collaborate with architecture/design/software, mentor engineers, and ensure functional signoff and performance/power goals.

Lead innovative aircraft design projects using advanced tools. Focus on systems engineering across disciplines from conceptual design to flight testing.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.

Drive verification from architecture/design to production silicon by developing scalable methodology, creating testbenches and portable tests, executing subsystem and full-chip verification, achieving coverage closure, and leading reviews toward sign-off, tapeout, and silicon bring-up.

Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.

The Senior Principal Engineer will define and develop system architectures for high-speed industrial products, collaborating closely with customers and stakeholders. Responsibilities include product definition, development, and support, along with participation in business development and technical troubleshooting.

Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.

Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and review test plans, develop test harnesses and sequences, run regressions and close code/functional coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs.

Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.

Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and execute test plans, develop testbenches and harnesses, run regressions, close coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for space-qualified ASICs.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.

Design Verification Engineer responsible for test planning, verification, debugging, adversarial testing, and writing verification environments using HVLs and methodologies (UVM/RVM/OVM). Works with RTL, assertions, code coverage, and simulation acceleration tools; strong communication and scripting skills required.

Design and implement production-grade backend services and platform APIs in Go. Build Kubernetes-native components (controllers, operators, CRDs, webhooks), integrate with CI/CD, observability, and security systems, and apply AI/agentic programming to automate platform workflows and improve developer productivity. Troubleshoot distributed systems and participate in architecture reviews.

Design and document low-voltage electrical hardware and system-level circuitry for medical equipment. Gather requirements, produce high-level and detailed designs, perform power/analog/digital interface design and simulation, create schematics, support PCB/layout and harness development, and transition designs to production while following regulatory and safety standards.

Develop and execute FPGA/ASIC RTL verification tests and test plans using SystemVerilog/UVM. Review designs and RTL, analyze failures, write bug reports, and work with IP vendors and design/firmware engineers to resolve issues.

Develop and extend verification methodology for MAC-layer unit simulations and SoC environments. Architect and implement testbenches, APIs, golden reference models, 802.11 protocol generators/checkers. Define metrics and implement tests for functional correctness, coverage, and performance. Collaborate across teams and use scripting and simulator tools for debug and validation.

Verify complex hardware systems, including custom IP blocks and SoCs. Develop verification plans, testbenches, and maintain high coverage for reliable silicon.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The engineer designs analog and mixed-signal chips, manages layout processes, oversees verification plans, and runs complex simulations. Also responsible for guiding junior staff and consulting with users and vendors for alignment on project goals.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.

Manage and drive photonics layout and design automation, leading a team, ensuring quality, and facilitating cross-functional collaboration in a dynamic environment.