IC Design Verification Engineer

Posted 7 Hours Ago
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San Jose, CA, USA
In-Office
Senior level
Information Technology • Professional Services • Consulting
The Role
Develop and extend verification methodology for MAC-layer unit simulations and SoC environments. Architect and implement testbenches, APIs, golden reference models, 802.11 protocol generators/checkers. Define metrics and implement tests for functional correctness, coverage, and performance. Collaborate across teams and use scripting and simulator tools for debug and validation.
Summary Generated by Built In
Job Description

IC design verification engineer

San Jose, CA

Full time hire

Qualifications

Your primary job responsibility is to establish/enhance the verification methodology for unit-level MAC layer simulation and extend the methodology to SoC level simulation environments. In this role you will be architecting and implementing the infrastructure including test-benches, APIs, golden reference models, 802.11 specific protocol layer generators and checkers. You will also be responsible for establishing metrics and implementing tests for functional correctness, coverage, and performance characterization.

Typically requires a BSCS/BSEE degree and 8 years of related experience, an MSCS/MSEE degree and 6 years of related experience

Experience building UVM based verification environments – unit-level and SoC - for 802.11, Ethernet or other networking designs

Knowledge of wired or wireless networking protocols is desirable

Expert knowledge of HVLs: SystemVerilog/OVM/UVM is required and OO programming experience is a plus

Knowledge of assertion based (SVA, PSL based) methodologies – formal and simulation - is necessary

Experience in establishing and managing coverage requirements and achieving coverage metrics is desirable

Working knowledge of scripting in Perl, Python, Tcl, and C

Experience with logic simulators and debug tools from Cadence, Synopsys, and Mentor

Ability to effectively collaborate with multiple teams, across geographies, in a dynamic, fast paced development environment

Capability to learn new skills or technologies as needed and be self-motivated

Additional Information

All your information will be kept confidential according to EEO guidelines.

Skills Required

  • BSCS/BSEE with 8 years related experience, or MSCS/MSEE with 6 years related experience
  • Experience building UVM-based verification environments for unit-level and SoC (802.11, Ethernet or networking designs)
  • Expert knowledge of HVLs: SystemVerilog, OVM, UVM
  • Knowledge of assertion-based methodologies (SVA, PSL) for formal and simulation
  • Experience establishing and managing coverage requirements and achieving coverage metrics
  • Working knowledge of scripting in Perl, Python, Tcl, and C
  • Experience with logic simulators and debug tools from Cadence, Synopsys, and Mentor
  • Knowledge of wired or wireless networking protocols
  • Ability to collaborate across teams and geographies in a fast-paced environment; self-motivated and able to learn new technologies
  • Experience defining metrics and tests for functional correctness, coverage, and performance characterization
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The Company
125 Employees
Year Founded: 2005

What We Do

Founded in 2005, WinMax Systems Corporation is a professional services firm specializing in IT recruiting, technology talent acquisition, and management consulting. They provide value-driven talent and managed services, offering expertise in technology and business consulting across various verticals, including program, project, and financial management. They focus on connecting top tech talent with innovative organizations to maximize efficiency and complete projects on time and budget.

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