Top Design Engineer Jobs

Reposted 22 Days AgoSaved
In-Office
Waynesboro, VA, USA
79K-148K Annually
Senior level
79K-148K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design and develop test-focused hardware/software solutions including real-time data analytics, UI/UX, instrument drivers, firmware, and SW/HW integration. Verify requirements, troubleshoot anomalies, automate processes, and work in Agile/SDLC environments. Support product cost-conscious designs and special program access requirements.
Top Skills: AgileAmaxCC#C++Data AnalyticsFirmwareFpga ProgrammingHardware Driver DevelopmentInstrument DriversLabwindows CviPlc/HmiPythonRs Logix 5000Rs ViewRtosSdlcSoftware IntegrationUi/Ux
Reposted 22 Days AgoSaved
In-Office
Waynesboro, VA, USA
112K-168K Annually
Senior level
112K-168K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Lead mechanical/test design for electromechanical systems including panel, fixture, console, and component design; thermodynamic and cooling analysis; electromechanical integration; requirements verification; troubleshooting and anomaly resolution; support automated handling equipment, RF receivers, and lab test setups. Role requires clearance eligibility and on-site presence.
Top Skills: DfmDmmGd&TNx 10OscilloscopePlc/HmiRs Logix 5000Rs View
Reposted 22 Days AgoSaved
In-Office
Baltimore, MD, USA
88K-163K Annually
Senior level
88K-163K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design, model, and verify RF/microwave and mixed-signal assemblies and subsystems using EM simulation and prototyping. Manage RF budgets, frequency planning, materials and packaging tradeoffs, and collaborate with mechanical, manufacturing, quality, supply chain, and test teams. Support product lifecycle from prototyping through production and sustainment; develop custom RF ICs and predict assembly-level performance.
Top Skills: AltiumAnsys HfssAnsys MaxwellCst MicrowaveEaglewareFekoGenesysKeysight AdsTicraXpedition
Reposted 22 Days AgoSaved
In-Office
Waynesboro, VA, USA
112K-168K Annually
Senior level
112K-168K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design and develop integrated hardware test solutions including console and panel layouts, power/cooling monitoring, RF and electronic circuit design. Support SW/HW integration, requirements verification, lab testing, anomaly investigation, and documentation. Lead technical work while ensuring cost, schedule, and producibility constraints are met.
Top Skills: AteCC++CapitalDigital MultimeterHigh-Speed Digital DesignLabwindows CviLvdsMentor GraphicsNetwork AnalyzerOscilloscopePcb LayoutPxiPxieRf TheoryTeststandVmeZuken
Reposted 22 Days AgoSaved
In-Office
Waynesboro, VA, USA
153K-229K Annually
Expert/Leader
153K-229K Annually
Expert/Leader
Aerospace • Logistics • Security • Software • Cybersecurity
Design and implement HW/SW test and instrumentation solutions including real-time data analytics, UI/UX, instrument drivers, firmware, and SW/HW integration. Support requirements verification, anomaly investigation, process automation, and design-to-cost considerations in an Agile environment.
Top Skills: AgileAmaxCC#C++FirmwareFpgaFpga ProgrammingHardware Driver DevelopmentLabwindows CviPlc/HmiPythonRs ViewRslogix 5000RtosSdlcSw Integration
Reposted 22 Days AgoSaved
In-Office
Waynesboro, VA, USA
123K-184K Annually
Senior level
123K-184K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design and implement HW/SW test solutions including real-time data analytics, UI/UX, instrument drivers, firmware, PLC/HMI and SW/HW integration. Support requirements verification, anomaly investigation, process automation, and cost-conscious design in an Agile SDLC environment for mission-critical systems.
Top Skills: AgileAmaxCC#C++FirmwareFpgaFpga ProgrammingHardware Driver DevelopmentLabwindows CviPlc/HmiPythonRs ViewRslogix 5000RtosSdlcSoftware IntegrationUi/Ux
Reposted 22 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Aerospace
The Design, Stress & MRB Engineer will create solutions for manufacturing non-conformities and perform structural analysis for aircraft components.
Top Skills: CatiaDfemGfemGoogle SuiteIsamiMS Office
Reposted 22 Days AgoSaved
In-Office
Redondo Beach, CA, USA
140K-180K Annually
Senior level
140K-180K Annually
Senior level
Aerospace • Software
Lead standardization and implementation of design processes across structures, propulsion, avionics, composites, and mechanisms. Define margining, configuration management, release workflows (CAD→PLM→MRP/ERP), review templates, and design-for-reliability practices. Create tools for traceability and use build/flight data to influence requirements. Drive quality, containment, corrective actions, and cross-functional problem solving with build, quality, and flight reliability teams.
Top Skills: As9100CadErpFmeaGd&TIso 9001MrpPlmWeibull Analysis
Reposted 22 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Hardware
Provide strategic technical leadership for board-level hardware design across defense and aerospace programs. Architect high-speed digital boards (400G+ Ethernet, PCIe Gen5+, DDR5+), drive design-for-manufacturing/test, lead proposals and BOE, mentor engineers, and champion signal integrity, EMI, and reliability practices for ruggedized mission-critical systems.
Top Skills: 400G+ EthernetAmd Altera FpgasBroadcomCadence AllegroCascade LakeCom ExpressConfluenceDdr5+ SdramDo-160GDoorsDrfmEmerald RapidsEmi ComplianceFiber OpticsFmecaIntel Xeon-DIntel/Xilinx AgilexJamaJIRAMarvellMellanoxMil-Std-461GMil-Std-704FPcie Gen5+Sapphire RapidsStress DeratingVersalVideo InterfacesVita42Vita46Vita62Vita65
Reposted 22 Days AgoSaved
In-Office
3 Locations
Senior level
Senior level
Hardware
Lead design and development of ruggedized board-level hardware for defense/aerospace systems. Architect high-speed digital boards (FPGAs, secure processing, PCIe, DDR5, 400G Ethernet), establish design standards, ensure manufacturability and verification, support proposals, and mentor engineering teams through production.
Top Skills: 400G EthernetAmd VersalBroadcom (Network Interfaces)Cadence AllegroCadence ConceptCadence DehdlCascade LakeCom ExpressConfluenceDdr5DfaDfmDftDoorsFmecaGranite RapidsIntel Xeon-DIntel/Altera AgilexJamaJIRAMarvell (Network Interfaces)Mil-StdNvidia (Network Interfaces)Pcie Gen5Signal IntegritySomVitaVpxXilinx Versal
Reposted 22 Days AgoSaved
In-Office
3 Locations
Senior level
Senior level
Hardware
Lead board-level design of ruggedized, high-speed digital hardware from concept through production for defense/aerospace systems. Architect FPGA and CPU-based solutions, ensure signal integrity and manufacturability, establish design standards, support proposals, and collaborate with manufacturing for DFM/DFT.
Top Skills: 400G EthernetAmd/Xilinx VersalCad/Si ToolsCadence AllegroCadence Dehdl/ConceptCascade LakeCom ExpressConfluenceDdr5DeratingDfaDfmDftDoorsFmecaFpga (Xilinx VersalGranite Rapids)Intel Xeon (Xeon-DIntel/Altera Agilex)JamaJIRAMil-StdNvidia/Broadcom/Marvell Network InterfacesPcie Gen5Signal IntegritySystem On Module (Som)Vpx/Vita
Reposted 22 Days AgoSaved
In-Office
San Jose, CA, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.
Top Skills: AssertionsBfmBugzillaCC++DriverDspGate-Level SimulationMakeMonitorPerlPythonScoreboardSubversionSvtbSystemverilogUvm
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Reposted 22 Days AgoSaved
In-Office
Conroe, TX, USA
Mid level
Mid level
Hardware • Other • Energy
Design and develop solids control and waste management equipment using mechanical engineering principles. Perform FEA/CFD simulation, material selection, testing, validation, root cause analysis, and support product lifecycle and field reliability efforts while collaborating cross-functionally and mentoring junior engineers.
Top Skills: AbaqusAnsysCfdFeaSolidworks Simulation
Reposted 22 Days AgoSaved
Remote
Minnesota, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Design and execute SystemVerilog/UVM verification environments: plan verification, write constrained-random and directed tests, measure and close coverage, run gate-level sims, and automate regressions. Work includes C-based processor-in-loop tests, emulation, memory/MMU and DSP/memory-subsystem verification, and power-aware/formal methodologies when applicable.
Top Skills: Amba AhbAmba ApbAmba AxiCCadence XceliumConstrained-Random VerificationCpfEmulation (Cadence Palladium)Functional CoverageGate-Level SimulationMmuPerlPythonReal Number Models (Rnm)Siemens QuestaSramSva (Systemverilog Assertions)Synopsys VcsSystemverilogTclUpfUvm
Reposted 22 Days AgoSaved
In-Office
San Jose i California, CA, USA
87K-132K Annually
Senior level
87K-132K Annually
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Lead architecture and implementation of SoC design verification environments using SV/UVM. Develop constrained-random, self-checking testbenches, SoC test firmware in C/C++, automate verification flows, close coverage/regression, and support multi-million gate ASIC tapeout including formal verification and methodology improvements.
Top Skills: ArmAssertionsAxiCC++CoverageEthernetFormal VerificationNocPcieRegressionRisc-VSystemverilogUcieUvm
Reposted 22 Days AgoSaved
In-Office
San Jose i California, CA, USA
112K-171K Annually
Senior level
112K-171K Annually
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Responsible for DFT implementation for 3nm/5nm networking SoCs and IPs: RTL checks, scan insertion, ATPG (compressed/uncompressed), pattern simulation, MBIST and JTAG insertion/verification, silicon debug/bring-up, automation and scripting (Perl/Shell/TCL), and low-power DFT work.
Top Skills: 3Nm5NmAtpgCadence ModusDaertIeee 1149.1 JtagMakefileMbistMentor TessentPerlPllScan InsertionSerdesShellSocSynopsys SpyglassSynopsys TetramaxTclTestkompressVcsVerdi
Reposted 22 Days AgoSaved
In-Office
Mountain View, CA, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Implement and verify DFT for advanced-node (3nm/5nm) SoCs: scan insertion, ATPG (compressed/uncompressed), pattern simulation, MBIST insertion/verification, JTAG insertion, silicon bring-up, scripting and flow automation, and debug using Verdi/VCS.
Top Skills: 3Nm5NmAtpgCadence ModusDftIeee 1149.1 JtagLow Power DftMakefileMbistMentor TessentPerlScan InsertionShellSynopsys SpyglassSynopsys TetramaxTclTessent TestkompressVcsVerdi
Reposted 22 Days AgoSaved
Remote
United States
Senior level
Senior level
Aerospace
The Senior Engineer will lead structural design efforts in the development of advanced aircraft, manage compliance with regulations, oversee multi-disciplinary trade studies, and mentor junior engineers.
Top Skills: 3Dx3Dx PlmCatia V5Dassault Composites WorkbenchEnoviaV6
Reposted 22 Days AgoSaved
Remote or Hybrid
2 Locations
Senior level
Senior level
Software
The engineer will develop high-speed analog ICs, oversee product development phases, and collaborate with various engineering teams to ensure product performance and reliability.
Top Skills: Cad Scripting Languages (SkillCmosHigh-Speed Analog Ic DesignPythonShell Scripts)Sige BicmosVeriloga
Reposted 22 Days AgoSaved
In-Office
Charlotte, NC, USA
Senior level
Senior level
Information Technology • Software
Lead mechanical project engineering for facility projects: assess building systems, develop equipment specifications and construction drawings, produce proposals, manage submittals, provide on-site engineering and commissioning, perform PE review/stamping, coordinate MEP engineering, and document project deliverables.
Top Skills: AutocadBuilding Automation SystemsHvacMS OfficeRevit
Reposted 22 Days AgoSaved
In-Office
Hanahan, SC, USA
Entry level
Entry level
Information Technology • Software
Assist the Project Engineer with MEP design and development: survey building systems, perform load calculations, develop equipment specifications and construction drawings, support submittal reviews, drafting and BIM modeling, prepare MEP assessments and engineering reports, provide on-site engineering support, coordinate prefabrication/shop drawings, and maintain project documentation.
Top Skills: AutocadBimBuilding Automation SystemsHvacMS OfficeRevit
Reposted 22 Days AgoSaved
In-Office
Hanahan, SC, USA
Senior level
Senior level
Information Technology • Software
Lead mechanical project engineering for facility HVAC/MEP projects: survey systems, create specs and construction drawings, manage submittals, support commissioning, provide on-site engineering, prepare proposals and reports, and stamp PE work as required.
Top Skills: AutocadBuilding Automation SystemsHvacMS OfficeRevit
Reposted 22 Days AgoSaved
In-Office
Delaware, OH, USA
Senior level
Senior level
Hardware • Software • Analytics
Lead mechanical architecture and system integration for rack- and row-based data center infrastructure. Own 3D CAD design, perform/coordinate FEA and validation testing, ensure manufacturability and compliance, drive cross-functional reviews, support factory integration and pre-sales, and mentor junior engineers.
Top Skills: 3D CadCreoFea Tools
Reposted 22 Days AgoSaved
In-Office
San Diego, CA, USA
214K-348K Annually
Senior level
214K-348K Annually
Senior level
Semiconductor • Appliances
Responsible for digital ASIC design architecture, project management, and implementation of verification and validation processes for mixed signals ICs.
Top Skills: AmbaCadenceCmosDigital Asic DesignFpgaRisc-VRtl DesignSynopsysSystem VerilogVerilog
Reposted 22 Days AgoSaved
In-Office
Chandler, AZ, USA
57K-139K Annually
Senior level
57K-139K Annually
Senior level
Hardware • Semiconductor
Lead and implement physical design tasks for 32-bit microcontroller and wireless products, including floorplanning, placement optimization, clock tree synthesis, routing, timing closure, multi-voltage floorplans, verification-clean designs, flow automation, and vendor/IP interfacing while collaborating with international teams.
Top Skills: Clock Tree SynthesisCrosstalkEmirLogic SynthesisLow Power MethodologiesPhysical DesignPhysical VerificationPlace And RoutePythonRtlTclTiming ClosureVerilogVhdlVlsi
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