Top Hardware Engineer Jobs in Sacramento, CA

Develop and maintain transistor-level timing characterization flows for custom IP, memories, SRAMs, register files, and compiler-generated macros. Build CAD infrastructure, automation, and validation methodologies for timing, power, and noise models. Collaborate with circuit design, memory, STA, methodology, and EDA vendor teams. Support hardware design, verification, integration, layout, and timing development for advanced semiconductor technology nodes.

Maintains and troubleshoots server, storage, networking, cabling, and power hardware across a large-scale production data center fleet. Writes Python automation scripts, reviews logs and alerts, performs diagnostics, supports deployments, builds hardware health dashboards, coordinates with DevOps, supply chain, and vendors, and assists with hardware evaluation and reliability improvements. Requires on-call availability and travel to data center sites.

Designs and verifies ultra-high-speed PCB circuits and new routing-system hardware for Nokia’s Service Router products. Responsibilities include schematic and board design, simulation, design verification, production release, board bring-up, debugging, and hardware-lab testing. The role also maintains hardware and system integrity while collaborating with engineering teams to deliver reliable high-performance digital hardware.

Deliver global NAND test tooling hardware solutions for wafer and package testing. Collaborate with customers and distributed product development teams to identify hardware requirements, meet development schedules, and support sustainability and evolving NAND roadmap needs. The role requires developing and delivering semiconductor tooling hardware using mechanical or electrical engineering expertise and CAD/PCB design applications.

Design and develop wireless power transfer and energy-harvesting hardware for IoT and wearable devices. Apply power electronics, RF and electromagnetic theory to create ICs and circuits, integrate solutions into scalable systems, optimize energy efficiency, and drive sustainable innovation for large sensor networks.

Designs and validates electrical and electronic components, subsystems, integrated circuitry, and hardware solutions. Develops test plans covering tolerances, form, fit, function, shock, vibration, EMI, safety, reliability, thermal performance, and power. Performs feasibility, margin, validation, modeling, and empirical analyses; collaborates with internal and outsourced engineering partners; evaluates production reliability and supports prototype fabrication for reliable, cost-effective products.

Tests, validates, and troubleshoots next-generation cloud server hardware for performance, power, reliability, and quality. Develops test scripts, documents results, identifies defects, recommends improvements, and resolves hardware issues across engineering and manufacturing environments. Requires hands-on embedded systems debugging, Linux and scripting experience, and knowledge of server architecture, firmware, operating systems, networking, storage, and hardware acceleration technologies.

Develop and operate Akamai’s Linux-based cloud infrastructure, including bare-metal and virtual machine platforms, kernels, operating systems, and KVM/QEMU virtualization. Build software, automation, observability, and infrastructure enhancements at scale; troubleshoot complex distributed-system issues; collaborate across engineering and operations; mentor team members; and participate in on-call service restoration.

Designs and maintains high-speed digital hardware for Nokia Service Router products. Responsibilities include ultra-high-speed PCB circuit design, simulation, verification testing, board bring-up, laboratory debugging, and taking complex board designs from concept through production release. The role requires collaboration with engineering teams, ownership of hardware integrity, and practical use of oscilloscopes, logic analyzers, and digital debugging tools.

Designs and develops FPGA SmartNIC networking acceleration for Microsoft Azure. Responsibilities include hardware architecture evaluation, RTL coding in Verilog/SystemVerilog, simulation, hardware testing, debugging, verification, scripting, software development, Agile collaboration, and production DevOps support. The role partners across hardware and software teams to deliver cloud networking infrastructure, including SDN capabilities, packet manipulation, and performance improvements.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

Designs electrical control systems for conveyor and material-handling equipment, including power calculations, 480V and 120V schematics, I/O drawings, PLC and panel layouts, field-device layouts, and material specifications. Collaborates with customers, sales engineers, and project managers to define requirements. Inspects, tests, commissions, and troubleshoots motor control panels for compliance with design standards, codes, and project specifications.

Owns the hardware lifecycle for GPU and infrastructure assets, including fleet health monitoring, vendor RMA workflows, firmware and BIOS upgrades, burn-in testing, failure investigation, inventory accuracy, capacity planning, spare-parts strategy, runbook creation, and new platform qualification. The role serves as the technical owner of physical compute platforms and supports high-density GPU infrastructure across sites.

Develop and own compute and GPU server platforms from architecture through global deployment. Responsibilities include schematic and layout reviews, design for manufacturability, new product introduction, board and system bring-up, validation, debugging, firmware and BIOS feature management, technology qualification, and vendor coordination. The role requires hands-on server architecture, board-level design, Linux and scripting expertise, platform validation, and five-day-per-week presence in the Cambridge office.

Pipeline hiring for hardware engineers at all experience levels. Work includes circuit board design, schematic capture, component selection and prototype bring-up, hardware debug/testing and failure analysis, integration with firmware/software teams, and design for manufacturability with production handoff.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Debug and resolve complex hardware/software issues for manufacturing test stations. Lead commissioning and release-to-manufacturing of opto-electrical test stations, improve test uptime, provide documentation and support to contract manufacturers and vendors, coordinate equipment RFQs/RMAs, and use AI tools for data analysis.

Design and develop system power hardware for next-generation networking platforms, from component selection and schematic design through board bring-up, debugging, validation, testing, margin analysis, and root-cause analysis. Collaborate with cross-functional teams to ensure robust, manufacturable, high-performance power delivery.

Lead end-to-end hardware design for high-speed Ethernet switches: author specs, select components, capture schematics, collaborate on PCB layout and SI/PI simulations, specify stackups, work with contract manufacturers, perform lab bring-up and complex system debug with software/test teams, drive DFM for production, and mentor junior engineers.

Design and optimize high-speed, high-density ASIC package layouts and substrate breakouts. Perform pinout optimization, routing, placement, stack-up, power distribution, CAD library development, feasibility studies, and productivity methodology improvements while collaborating with package leads and cross-functional teams.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.