Top Design Engineer Jobs

Leads semiconductor design transfer programs, troubleshooting device behavior differences between manufacturing sites, assessing circuit and test impacts, supporting simulations and risk assessments, enabling foundry design environments, and modifying GDS files for tape-in and tape-out projects. Requires deep semiconductor design, device modeling, process design rule, chip architecture, yield improvement, failure analysis, and CAD layout expertise.

Develop and integrate software, data pipelines, LIMS infrastructure, dashboards, instrument controls, and automated assay workflows for an ultrasensitive immunoassay platform. Execute system verification tests, baseline assays, and calibration studies while troubleshooting hardware, software, and reagent interfaces. Translate assay insights into software requirements and maintain compliant documentation under 21 CFR Part 11, ISO 13485, and FDA QSR design controls.

Leads verification strategy and execution for complex semiconductor memory interface designs. Develops and optimizes SystemVerilog/UVM testbenches, test plans, coverage strategies, constrained-random tests, checkers, and reusable verification components. Owns verification from planning through signoff, drives debugging and coverage closure, collaborates with RTL and design teams, identifies technical risks, and mentors verification engineers while supporting next-generation DDR technology.

Leads verification strategy and execution for complex semiconductor memory interface designs at block and system levels. Develops and optimizes SystemVerilog/UVM testbenches, test plans, coverage strategies, checkers, and constrained-random testing. Owns verification from planning through signoff, drives debugging and coverage closure, partners with RTL engineers, improves verification methodologies, and mentors verification engineers while communicating technical risks and readiness to leadership.

Provides technical leadership for verification of complex semiconductor memory interface designs. Defines verification strategies, test plans, coverage goals, and scalable SystemVerilog/UVM environments; drives constrained-random testing, functional coverage, debugging, coverage closure, and signoff. Partners with RTL and design teams to resolve issues, improve verification efficiency, and ensure functional and performance requirements are met. Mentors verification engineers and communicates technical risks, progress, and readiness to engineering leadership.

Provides technical leadership for semiconductor design verification at block and system levels. Defines verification strategies, test plans, coverage goals, and UVM environments; leads constrained-random testing, debugging, coverage closure, and signoff. Partners with RTL and design teams, develops reusable verification components, improves methodologies, and mentors engineers. The role focuses on next-generation DDR6 memory interface products and data buffer silicon.

Lead verification strategy and execution for complex semiconductor memory interface designs at block and system levels. Architect SystemVerilog and UVM environments, develop test plans, drive constrained-random testing, functional coverage, debugging, and coverage closure, and own verification through signoff. Collaborate with RTL and design teams, improve methodologies and reuse, resolve complex failures, mentor engineers, and communicate technical risks and readiness to stakeholders.

Develop and execute verification strategies for analog and mixed-signal ICs. Responsibilities include creating verification plans, test benches, tests, simulations, behavioral models, regression scripts, and coverage analyses at RTL and gate level. The role tracks verification status and closure, collaborates with analog, digital, and systems engineering teams, and improves design verification methods, tools, and workflows.

Designs, analyzes, prototypes, and tests mechanical and aerospace systems for defense and industrial applications. Creates CAD models and manufacturing drawings, performs stress analysis and tolerance stack-ups, leads prototype manufacturing and testing, evaluates results, and recommends improvements. Coordinates with multidisciplinary teams, vendors, and technicians; manages schedules, costs, and deliverables; and ensures compliance with GD&T, DoD standards, safety regulations, and quality requirements.

Performs functional verification of GPU graphics, media, and display logic through reusable test benches, verification plans, system simulations, and coverage-driven testing. Debugs pre-silicon failures, analyzes power and timing, implements corrective measures, and collaborates with architecture, RTL, and physical design teams. Maintains verification infrastructure, documents plans, and leads technical reviews.

Support Body In White (BIW) and Closures engineering across concept, production design, release, and manufacturing. Create and maintain APQP documentation (DVP&R, DFMEA), define sourcing docs, maintain CTDS, support CAE/FEA, testing, manufacturing, quality, and supplier launch activities. Provide detailed mechanical engineering work, progress reporting, benchmarking, and cross-functional collaboration with AME, design studio, and global teams.

As a Senior Design Engineer, you will design robotic hardware, conduct simulations, collaborate with teams, manage vendor relationships, and mentor junior talent.

Leads Body in White vehicle engineering and design release activities from development through production. Responsibilities include CAD and CAE data release, subsystem design, benchmarking, target achievement, regulatory compliance, DVP&R and DFMEA review, production feasibility, supplier coordination, global milestone meetings, complex problem solving, and technical team development. The role supports complete vehicle launches and ensures designs meet performance, cost, quality, timing, safety, and manufacturing requirements.

Lead design verification for complex ASIC and SoC connectivity silicon. Develop verification plans, UVM-based SystemVerilog testbenches, assertions, scoreboards, coverage models, and regression automation. Verify PCIe, UALink, and UCIe switching behavior through directed and constrained-random testing. Debug simulation failures, close functional and code coverage, support issue isolation and silicon bring-up, and communicate verification status, risks, and recommendations to technical stakeholders.

Develop and execute verification strategies for connectivity ASICs and SoCs supporting PCIe, UALink, and UCI protocols. Build UVM-based SystemVerilog testbenches, test scenarios, assertions, scoreboards, and coverage models. Debug simulation failures, drive functional and code coverage closure, automate regressions, and collaborate with architecture, RTL, firmware, design, and post-silicon teams on root-cause analysis and silicon readiness.

Design and deliver mechanical hardware for collaborative robots from concept through testing. Responsibilities include developing structures, enclosures, electromechanical packaging, thermal management, and environmental protection; collaborating with hardware, safety, manufacturing, test, and suppliers; and owning CAD, analysis, prototyping, validation, troubleshooting, root-cause analysis, and design iteration. The role is onsite in Santa Clara and requires occasional travel and U.S. person status.

Designs, develops, and maintains high-performance full-stack Order Management System features for financial trading applications. The role focuses on Java backend development, frontend functionality, scalability, low latency, troubleshooting, architecture, code reviews, mentoring, and technical collaboration with product and engineering teams.

Design and analyze digital and analog circuits for HBM/DRAM products, including simulation, optimization, floorplanning, timing/area/power trade-offs, full-chip and block-level functional evaluation, architecture pathfinding, and collaborating on memory, logic, and analog circuit development. Leverage AI for research and design tasks.

Supports civil and structural engineering design and construction for municipal water supply and wastewater infrastructure. Responsibilities include preparing drawings, calculations, specifications, technical documents, and change orders; conducting field investigations; reviewing shop drawings and requests for information; assisting with project schedules; coordinating with engineers and stakeholders; and documenting issues and resolutions.

Own and build production UI for a fund administration product: design and implement dense, high‑stakes financial workflows, prototype in code, define and maintain the design system, and create human–AI interaction patterns for human-in-the-loop review. Partner closely with product, ops, customers, and engineering to translate complex workflows into polished, trustworthy interfaces.

Leads mixed-signal verification for automotive PMIC products, designing RNM and AMS environments, developing verification strategies, and managing RTL, gate-level, timing, power, and PVT simulations. Debugs analog and digital interactions, supports automotive safety compliance, and collaborates with design, ATE, application engineering, and silicon validation teams. The role also mentors engineers, improves verification methodologies and infrastructure, and evaluates emerging and AI-based verification technologies.

Leads mechanical architecture and system-level design for precision semiconductor wafer probing and test platforms. Responsibilities include developing motion, chucking, wafer handling, mechatronic, structural, thermal, and dynamic systems; conducting FEA and tolerance analysis; driving product development through production; resolving complex technical issues; supporting installations and qualification; and providing cross-functional technical leadership and mentorship.

Designs and reviews NVIDIA GPU and Tegra-based product boards across servers, automotive, robotics, industrial, and consumer applications. Collaborates with architects and cross-functional teams to optimize cost, performance, and schedules; prepares manufacturing documentation; develops improved circuits and functions; and enhances design workflows. Requires extensive board design experience, PCB review expertise, laboratory measurement skills, Linux and Windows proficiency, and strong communication abilities.

Lead mechanical architecture and product design for next-generation electronic products from concept through production. Develop structures, displays, acoustic, battery, antenna, and thermal systems; research materials and manufacturing processes; collaborate with industrial design; and lead internal teams, suppliers, consultants, and manufacturing partners. Apply DFM, DFA, GD&T, tolerance analysis, CAD, statistical methods, and mechanical engineering analysis across diverse consumer, automotive, and computing products.

Design and architect advanced aerospace computing electronics, including processor- and FPGA-based systems, high-speed interfaces, power systems, and radiation-mitigated circuitry. Lead schematic development, component selection, electrical analysis, PCB layout oversight, prototype bring-up, troubleshooting, verification, qualification, and production transition. Support environmental and radiation testing, root-cause investigations, technical reviews, and customer discussions. Mentor junior engineers and collaborate across FPGA, software, mechanical, manufacturing, quality, and integration teams.