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The Network Design Specialist is responsible for developing network specifications and design documents, ensuring customer alignment with desired solutions, and validating network configurations. This role includes physical and logical design, project support, and detailed documentation such as test and verification plans.
Manage and optimize VLSI development infrastructure, develop automation scripts, create performance dashboards, and collaborate with a remote team for infrastructure-related tasks.
The Wireless Modem Design Verification Engineer is responsible for digital ASIC and FPGA verification, developing test plans, automating test case generation, and contributing to pre-silicon and post-silicon validation. The role involves collaboration with cross-disciplinary teams to improve connectivity solutions for SpaceX's Starlink network.
As a Design Verification Engineer, you will develop and execute test plans for ASICs and FPGAs, ensuring digital designs are verified at block and system levels. Responsibilities include writing test sequences, developing test harnesses, automating test case generation, and contributing to pre-silicon and post-silicon validation efforts within the Starlink project.
As a Design Verification Engineer at SpaceX, you will verify digital ASIC and FPGA designs, develop test plans using SystemVerilog, automate testing with Python and MATLAB, and contribute to the pre-silicon and post-silicon validation processes for next-generation technologies.
The Sr. Design Verification Engineer will be responsible for verifying digital ASICs and FPGAs, developing test plans, conducting regressions, and contributing to pre- and post-silicon validation efforts to ensure complex digital designs meet performance requirements.
The Sr. Design Verification Engineer is responsible for verifying digital ASIC and/or FPGA designs, developing test plans, executing test sequences, and ensuring comprehensive validation of complex digital circuits. This role involves collaboration with cross-disciplinary teams to enhance the Starlink network's capabilities.
Body Engineering is seeking a Design Quality Technical Specialist to work within the Craftsmanship team supporting Design Quality activities related to appearance approval for luxury electric vehicles at Lucid. Responsibilities include reviewing and validating parts, coordinating with suppliers, and supporting quality teams. The role requires 8+ years of experience, a Bachelor's degree in Mechanical or Design Engineering, and strong technical understanding of automotive processes.
The Sr Design Quality Engineer will lead Design Quality activities for Lucid Air's parts, ensuring mold quality and approval for the PPAP process. Responsibilities include reviewing pre-grain parts, documenting issues, coordinating with suppliers, and mentoring junior colleagues, while actively supporting the craftsmanship team in achieving and maintaining high visual and dimensional standards.
The Sr Design Quality Engineer will lead design quality activities for customer-facing parts of the Lucid Air, ensuring quality and compliance during the PPAP process. Responsibilities include reviewing molded parts, coordinating shipments, assessing visual targets, documenting issues, and mentoring junior colleagues, while supporting the CMF team for colour matching.
The Principal QA Design Transfer Engineer supports quality engineering for medical device products, ensuring compliance with quality requirements and optimizing systems and documentation. Responsibilities include guiding design teams, conducting risk management activities, reviewing engineering changes, mentoring staff, evaluating manufacturing environments, and implementing improvements for quality assurance.
The R&D Senior Design Assurance Quality Engineer I will support design assurance and quality engineering for medical devices, ensuring compliance with quality standards while participating in product development processes. Key responsibilities include risk management and analysis, design control oversight, mentoring engineers, and improving quality systems and documentation.
The role involves developing silicon products for datacenters and AI/ML platforms. Responsibilities include logic synthesis, physical design, power optimization, and timing analysis with a focus on high-speed chip implementations in 5nm/3nm technology.
As a Principal Software Engineer - Front End and UX Design Systems at Procore, you will drive strategic direction and lead architectural design for technology initiatives. You will mentor team members, collaborate with various internal groups, and contribute to both core and independent projects. Your focus will be on creating high-performance, scalable solutions that align with customer needs and enhance their experience with Procore's construction intelligence software.
The Senior Design Verification Engineer will lead the verification of ARM-based SOCs for advanced perception applications. Responsibilities include developing verification environments, executing test plans, analyzing coverage, and working with cross-functional teams to ensure timely, high-quality SOC delivery.
The Sr. Engineer, Design Quality Assurance is responsible for overseeing design control processes, ensuring compliance with FDA and ISO standards, and addressing engineering issues in medical device development. The role includes guiding engineering staff, reviewing design documents, and implementing quality management procedures.
The role involves leading the design of Analog IC products, specifically CMOS transceiver/SERDES/PLL circuits. Responsibilities include architectural investigations, implementation, and design verification while managing delivery with a team of design engineers.
This role involves designing analog circuits for high-speed SerDes development using advanced technology nodes. Responsibilities include collaborating on architecture, instructing layout engineers, IP characterization, and validating designs.
The Senior Staff Engineer in Design QA will lead Design Assurance and Quality Engineering for new product development in Hardware and Embedded Software Systems. Responsibilities include ensuring compliance with standards, providing oversight for design deliverables, and supporting quality improvement initiatives throughout the development lifecycle.
The Principal Design Verification Engineer at Marvell will verify complex SoCs through RTL and gate level simulation, develop verification environments using System Verilog and UVM, manage tests and regression failures, and collaborate with teams to implement verification test plans.
Working as an Analog IC Design Staff Engineer at Marvell, responsible for high-speed and high-performance SerDes development in advanced technology nodes. Collaborate with design teams, provide instructions, support for IP usage, and validation. Must have a Master's degree or PhD in Electrical Engineering with strong knowledge in CMOS technologies, mixed signal circuit design, low power, and high-speed design techniques.
The Design Verification Engineer will ensure the successful development of test benches for Etched's first ASIC, focusing on scalable testing methods. They will work closely with the engineering team to guarantee deliverables meet quality and performance standards while being passionate about modern AI technologies.
The Principal Design Verification Engineer will develop ASIC testbenches, implement micro-architecture using System Verilog, and collaborate with design teams to ensure microchip functionality. Responsibilities include executing functional verification, applying timing closure methods, utilizing formal verification tools, debugging designs, and documenting the verification process.
As a Design Verification Engineer, you will ensure the quality of digital designs through comprehensive verification methodologies, collaborating with design teams, writing and executing test cases, and mentoring junior engineers.
The Design for Test Engineer will implement DFT features from RTL to tapeout for high-performance AI/ML architectures, focusing on cost reduction, debugging, and yield learning while collaborating with experienced engineers on various ASIC domains.
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