Top Design Engineer Jobs

Develop and validate block-level and full-chip SDC timing constraints and perform STA to identify and resolve timing issues. Collaborate with front-end and back-end teams on clocking, timing exceptions, and physical design closure. Optionally perform RTL design or IP integration and contribute to full-chip clocking documentation and SDC methodology to ensure correctness early in the design cycle.

Lead and define ASIC verification strategy and methodology across programs. Architect scalable verification infrastructure, mentor teams, drive cross-functional improvements, influence ASIC design for verifiability, and lead root-cause analysis during bring-up and post-silicon validation.

Lead verification strategy and execution for complex ASIC/SoC programs. Architect scalable UVM/SystemVerilog-based verification infrastructure, drive emulation/prototyping and formal verification, mentor teams, influence ASIC design for testability, and lead root-cause analysis during silicon bring-up and post-silicon validation.

Design and run automated tests for PIC devices and modules, develop test algorithms and calibration procedures, define and execute design verification plans, produce verification documentation, and support PIC-level failure analysis and production yield improvement.

Design and maintain block/cluster/top-level ASIC verification environments, build reusable testbenches, create and run constrained-random and directed tests, implement coverage, run gate-level simulations, support emulation and post-silicon bring-up, and collaborate with designers and software teams to debug complex chip issues.

Develop and architect ASIC design verification infrastructure, create and execute simulation-based test plans, build testbench components (scoreboards, agents, sequencers, monitors), perform block-to-chip level verification, coverage and performance analysis, debug designs, and collaborate with hardware, software, architects, and vendors.

Lead design and specification of high-efficiency DC-DC switch-mode power supplies and power delivery architectures. Perform simulation, component selection, layout guidance, thermal and noise optimization, lab bring-up, debugging, and verification. Collaborate cross-functionally with hardware, mechanical, optics, and manufacturing teams and create/execute test and DVT plans.

Design and execute ASIC verification for high-end switching products. Develop simulation models, test plans, directed and random tests, coverage, multi-chip/system simulation, and performance analysis. Build testbench components (scoreboard, agents, sequencers, monitors) and collaborate with hardware, software designers, and vendors.

Develop design solutions for new and existing products, engage with manufacturing, ensure design integrity, perform analyses, and manage projects.

The Senior Mechanical Design Engineer will design and optimize piping systems, perform fluid dynamics analysis, ensure project compliance, and mentor junior engineers.

Lead microarchitecture and RTL design of on- and off-chip interconnects (NoC, switches, bridges, protocol adapters) for a custom AI accelerator SoC. Drive RTL implementation, verification strategy, performance analysis, physical-design convergence, bring-up, and production readiness. Mentor junior engineers, manage third-party IP engagements, and collaborate across architecture, verification, physical design, firmware, and post-silicon teams to deliver scalable, high-performance interconnect fabrics.

Develop and execute mixed-signal IP verification plans, build UVM/OVM testbenches, perform analog behavioral modeling, debug presilicon issues, analyze coverage, and collaborate cross-functionally to meet design, power, and performance targets.

The Test Engineer is responsible for planning, developing, and executing test activities for reactor technologies, coordinating with engineers, overseeing test lifecycle, and documenting results.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVA, apply constrained-random and directed tests, run simulations, triage failures, drive root-cause analysis, maintain coverage and regression suites, and collaborate with cross-functional teams through sign-off.

Develop cutting-edge delta-sigma ADC products; contribute to digital design and embedded firmware, collaborating with analog designers and engineers.

Responsible for the design and testing of RF products, including requirements analysis, system design, and troubleshooting of electrical issues. Must collaborate with a team to enhance existing systems and create new solutions.

The Staff Digital ASIC Designer will design, implement, and verify digital signal processing and system-on-a-chip logic, integrating embedded processors and developing efficient on-chip data paths.

The role involves executing design assurance reviews and software quality assurance activities for aerospace systems, ensuring compliance with safety standards and regulations, while also engaging with certification authorities and improving internal processes.

Design and optimize engine mechanical systems for the Symphony jet engine, collaborating with cross-disciplinary teams and ensuring integration across aircraft systems.

The Senior Engineer manages product life cycles post-launch, analyzing changes, ensuring regulatory compliance, providing technical support, and mentoring junior engineers.

The SoC/ASIC Design Verification Engineer will verify silicon design in security-sensitive settings, engage with customers, and develop verification collateral for secure silicon.

Develop CAD software and methodologies for high performance chip design and verification at NVIDIA. Collaborate on EDA tools and provide project support.

Design and implement algorithms and tools for chip-level placement, reshaping, and global routing. Develop computational geometry, placement, routing and graph-optimization solutions, apply machine learning for design space exploration, extend GUIs for debugging/visualization, and collaborate with design teams to deploy high-performance C++ tools impacting next-generation AI chip physical layouts.

Verify digital design, golden models and micro-architecture of SerDes IPs using UVM/VMM and SystemVerilog. Build BFMs, monitors, checkers and scoreboards, define verification scope and infrastructure, write test plans, execute coverage-driven and assertion-based verification, and collaborate with architects, designers and pre/post-silicon teams to ensure product-quality delivery on compressed schedules.