Broadcom

RTL Design Engineer

Reposted 13 Days Ago

Be an Early Applicant

2 Locations

In-Office

127K-203K Annually

Expert/Leader

Software • Semiconductor • Manufacturing

The Role

Lead digital architecture, design, synthesis and verification of RTL for AMS/IO subsystems. Drive timing closure, lint/CDC debug, formal verification, DFT insertion, and generate timing constraints. Collaborate across analog, verification, and SoC teams, produce specifications and verification plans, and support advanced-node/FinFET designs.

Summary Generated by Built In

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Job Description:

Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

Define the digital architecture and verification strategies for complex AMS and IO subsytems
Design, synthesis, and verification of Verilog/SystemVerilog RTL.
Analysis, debug, and resolution of Lint and CDC issues in the design.
Design convergence to timing closure utilizing RTL optimization strategies.
Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
Drive comprehensive test plans to ensure quality of design.
Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
Create and maintain detailed specification, design, and verification documentation.

Job Requirements

MS +10 years of relevant industry experience.
Experience with digital implementation flow from RTL synthesis to timing closure.
Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
Experience with Tessent tool for DFT insertion and verification
Proficient with Perl, Python and Tcl scripting.
Strong problem solving skills with attention to detail.
Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications

Solid understanding of transistor-level circuit behavior.
Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

MS degree with 10+ years of relevant industry experience.
Design, synthesis, and verification of Verilog/SystemVerilog RTL.
Experience with digital implementation flow from RTL synthesis to timing closure.
Deep understanding of timing analysis with PrimeTime flow and generation of Liberty models.
Experience with Tessent tool for DFT insertion and verification.
Proficient with Perl, Python and Tcl scripting.
Analysis, debug, and resolution of Lint and CDC issues.
Conduct formal verification using Synopsys Formality or Cadence Conformal.
Generate timing constraints for synthesis and static timing analysis at block and SoC levels.
Strong problem solving skills and ability to work across internal and external engineering teams.
Solid understanding of transistor-level circuit behavior.
Familiarity with Cadence schematic/layout and SPICE/Spectre circuit simulation.
Experience with advanced FinFET process nodes and PPA tradeoffs.

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.