Top Design Engineer Jobs

Reposted 24 Days AgoSaved
In-Office
2 Locations
89K-134K Annually
Senior level
89K-134K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves physical design of complex chips, methodology development, running synthesis, place and route tools, and performing timing and EMIR analysis checks in a team setting.
Top Skills: Cadence GenusCalibreFormalityFusion CompilerIc CompilerInnovusLecPrimerailPrimetimeSynopsys Design CompilerTempusVoltus
Reposted 24 Days AgoSaved
In-Office
South Jordan, UT, USA
Senior level
Senior level
Healthtech • Other • Biotech
Provides quality engineering support for product design transfer in compliance with quality standards, coordinating risk management and conducting audits while mentoring team members.
Top Skills: 21 Cfr 820Iso 13485Iso 14791JmpLean ManufacturingMinitabOracleQuality Control ToolsSix SigmaStatistical Methodologies
Reposted 24 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Expert/Leader
150K-275K Annually
Expert/Leader
Artificial Intelligence • Hardware • Software
The DFT Engineer ensures efficient testability of ICs, develops DFT architectures, verifies implementations, and collaborates with teams for optimal production support.
Top Skills: Cadence Encounter TestEda ToolsMentor TessentPerlPythonSynopsys Dft CompilerSystem VerilogTcl
Reposted 24 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
150K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software
Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.
Top Skills: Hbm3PythonSystem VerilogVerilator
Reposted 24 Days AgoSaved
In-Office
2 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.
Top Skills: AtpgJtagSynopsys VcsSystemverilogUvmVerdiVerilog
Reposted 24 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Mid level
100K-500K Annually
Mid level
Hardware • Manufacturing
The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.
Top Skills: Ai Productivity ToolsIjtagSiemens TessentUvm
25 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
The Design Verification Engineer will verify cutting edge network switch routing designs, develop test plans, and execute verification processes for ASICs in networking applications.
Top Skills: Object Oriented Programming (Oop)PerlPythonSystemverilogUvmVerilog
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25 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
Responsible for verification of networking ASICs, including developing test plans, environments, and executing verification processes using SystemVerilog. Requires strong experience in digital design and verification techniques.
Top Skills: Object Oriented Programming (Oop)PerlPythonSystemverilogUvmVerilog
25 Days AgoSaved
In-Office or Remote
8 Locations
Senior level
Senior level
Artificial Intelligence • Robotics
The Mechanical Engineer will design and test robotic hardware, develop concepts, create 3D CAD designs, and support testing and integration.
Top Skills: 3D CadFea
25 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves verifying chip circuitry, developing test plans using UVM/System Verilog, debugging simulation failures, collaborating with engineers, and mentoring juniors.
Top Skills: C/C++System VerilogUvm
25 Days AgoSaved
In-Office
Durham, NC, USA
136K-265K Annually
Senior level
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The Senior Design Verification Engineer will collaborate on design verification strategies for GPU memory subsystems, perform verification using advanced tools, and enhance verification skills.
Top Skills: C++PythonSystem VerilogVerilog
Reposted 25 Days AgoSaved
In-Office
Hillsboro, OR, USA
122K-173K Annually
Mid level
122K-173K Annually
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
The engineer will validate IP features, create tests, debug failures, and develop tools for SOC integration and IP development.
Top Skills: LinuxObject Oriented ProgrammingOvmSystemverilogUnixUvmVerilog
Reposted 25 Days AgoSaved
Hybrid
Chandler, AZ, USA
Senior level
Senior level
Hardware • Software
Lead functional verification for mixed-signal ASICs including verification planning, UVM testbench development, constraint-random and directed tests, coverage and failure analysis, digital/mixed-signal modeling, gate simulations, and regression/debug infrastructure.
Top Skills: AvmGate-Level SimulationMixed-Signal ModelingOvmSystemverilogTestbench DevelopmentUvmVeraVerilogVerilog AssertionsVhdl
6 Months AgoSaved
In-Office
Detroit, MI, USA
110K-130K Annually
Senior level
110K-130K Annually
Senior level
Automotive • Hardware • Transportation • Manufacturing
The Senior Hardware Design Engineer will design and build innovative hardware systems, manage CAD models, develop manufacturing methods, and mentor junior engineers.
Top Skills: Siemens Nx
One Year AgoSaved
In-Office
Arlington, VA, USA
107K-140K Annually
Mid level
107K-140K Annually
Mid level
Edtech
The ASIC/FPGA Research Engineer will engage in digital hardware design, work with advanced prototypes, and support research efforts within a collaborative team setting.
Top Skills: C++GoLinuxPythonVerilogVhdl
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