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10 Days AgoSaved
In-Office
San Diego, CA, USA
137K-205K Annually
Senior level
137K-205K Annually
Senior level
Aerospace • Artificial Intelligence • Machine Learning • Robotics • Software
The Staff Engineer will design and integrate aircraft configurations for UAVs, focusing on aerodynamics and structural effectiveness in a multi-disciplinary team.
Top Skills: Cad Modeling (NxCfdFeaSolidworks)
Reposted 10 Days AgoSaved
In-Office
4 Locations
83K-122K Annually
Senior level
83K-122K Annually
Senior level
Industrial • Manufacturing
The role involves leading project engineering for material handling systems, collaborating with teams and customers, and ensuring project success.
Top Skills: 3D ModelingPlc ControlsSimulation And Modeling ToolsWcs SoftwareWms
Reposted 10 Days AgoSaved
Easy Apply
In-Office
Rochester, NY, USA
Easy Apply
95K-120K Annually
Senior level
95K-120K Annually
Senior level
Automation • Manufacturing
Lead and manage engineering projects, mentor teams, solve complex design challenges, ensure safety standards, and maintain client relationships.
Top Skills: CfdDeltek VisionFeaMicrosoft ProjectSolidworks
Reposted 10 Days AgoSaved
In-Office
2 Locations
126K-186K Annually
Senior level
126K-186K Annually
Senior level
Semiconductor
This role involves physical design of complex chips, integrating designs across disciplines, mentoring juniors, and scripting for automation.
Top Skills: Cadence InnovusEda ToolsPerlPythonShellTclVerilog
Reposted 10 Days AgoSaved
In-Office
Chaska, MN, USA
79K-116K Annually
Mid level
79K-116K Annually
Mid level
Healthtech • Manufacturing
The Design Assurance Engineer II will ensure compliance with quality standards, support product development, coordinate risk assessments, and assist in validation processes, while adhering to company values and regulatory requirements.
Top Skills: AnovaDoeFdaGauge R&RIsoMinitabSpc
Reposted 10 Days AgoSaved
In-Office
2 Locations
129K-206K Annually
Senior level
129K-206K Annually
Senior level
Artificial Intelligence • Internet of Things • Machine Learning • Semiconductor
This role involves validating SoC designs through functional logic verification, developing verification plans, analyzing performance, and collaborating with design teams.
Top Skills: C++JavaPerlPythonSystemverilogTclUvm
Reposted 10 Days AgoSaved
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In-Office
Huntsville, AL, USA
Easy Apply
Mid level
Mid level
Aerospace
The Mechanical Engineer II will design and analyze mechanical systems, draft technical drawings, participate in manufacturing, and perform testing and project management tasks.
Top Skills: CadCfdMachining ToolsMaterials ProcessingSoftware Design
Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
157K-243K Annually
Senior level
157K-243K Annually
Senior level
Semiconductor
Develop verification infrastructure for AI accelerator IP blocks, create test plans, debug, and mentor junior engineers in a collaborative environment.
Top Skills: C/C++PerlPythonSystem VerilogUvm
Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
219K-351K Annually
Expert/Leader
219K-351K Annually
Expert/Leader
Semiconductor
Lead verification strategy and methodologies for AI accelerators, define requirements, architect test benches, and support silicon bring-up.
Top Skills: C++SystemverilogUvm
Reposted 10 Days AgoSaved
Remote
15 Locations
145K-175K Annually
Senior level
145K-175K Annually
Senior level
Information Technology • Software
As Lead Electrical Engineer, you will oversee project design, construction, and coordination efforts, ensuring compliance with engineering standards and resolving design issues during construction.
Top Skills: Construction ManagementData Center DesignElectrical Engineering
Reposted 10 Days AgoSaved
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In-Office
Casa Grande, AZ, USA
Easy Apply
100K-110K Annually
Mid level
100K-110K Annually
Mid level
Aerospace • Information Technology • Software • Biotech • Design
As a Design and Release Engineer for Airbags, you will research, design, develop, and test airbag systems for vehicles. Responsibilities include analyzing proposals, collaborating with drafters, and maintaining product development history.
Top Skills: Computer Aided Design (Cad)
Reposted 10 Days AgoSaved
In-Office
2 Locations
60K-111K Annually
Mid level
60K-111K Annually
Mid level
Cloud • Hardware • Software • Semiconductor
Cadence is offering a 16-week paid returnship for Physical Design Application Engineers to update skills and re-enter the workforce after caregiving. Candidates will work with EDA tools on Digital Synthesis, Place and Route, and Signoff Analysis.
Top Skills: Digital SynthesisEda ToolsPhysical DesignPlace And RouteSignoff Analysis
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Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
103K-191K Annually
Senior level
103K-191K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The Lead Applications Engineer will architect memory solutions, provide technical presales support, present IP portfolio to customers, and evaluate performance of memory IP.
Top Skills: AxiDdr4Ddr5DfiFpgaGddr6Hbm2Hbm3Lpddr4Lpddr5MipiRtlSystem VerilogVerilog
Reposted 10 Days AgoSaved
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In-Office
Pittsburgh, PA, USA
Easy Apply
Senior level
Senior level
Fitness
The Lead UI Engineer will develop and maintain UI components, enforce design quality, and collaborate across teams to enhance the design system at Blink Health.
Top Skills: Ai-Assisted ToolsFigmaJavaScriptReactStorybook
Reposted 10 Days AgoSaved
In-Office
4 Locations
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Design Engineer will focus on chip-level physical architecture and integration for ASICs, optimizing die layout and collaborating with cross-functional teams to ensure successful designs meet performance targets.
Top Skills: CadenceLinuxPerlPythonRubyTcl
Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The role involves physical IC design, from RTL to silicon tape-out, including synthesis, verification, timing closure, and collaboration with RTL engineers.
Top Skills: Eda ToolsPerlTcl
Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Design Verification Engineer will develop verification environments using System Verilog and UVM, create verification components, analyze simulation failures, and produce test cases.
Top Skills: C/C++OvmPerlRtlSystem VerilogUvm
Reposted 10 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design interposer layouts for high-speed interfaces while collaborating with cross-functional teams. Requires scripting for automation and expertise in 2.5D/3D designs.
Top Skills: Cadence InnovusCadence IntegrityMentor Graphics CalibrePythonSkillSynopsys 3Dic CompilerTcl
Reposted 10 Days AgoSaved
In-Office
Fort Collins, CO, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Semiconductor
The Design Automation DFT Engineer will develop and support design automation software tools for ASIC development while collaborating with IC designers and EDA vendors to resolve issues.
Top Skills: BashC++PerlPythonRubyTcl
Reposted 10 Days AgoSaved
In-Office
Centennial, CO, USA
107K-203K Annually
Mid level
107K-203K Annually
Mid level
Aerospace • Travel • Manufacturing
As a Senior Propulsion Engineer, you'll lead the development of the Symphony compression system, design airfoils with CFD analysis, and analyze engine test data while collaborating with multidisciplinary teams.
Top Skills: AdsAxstreamCadNpssPycyclePython
11 Days AgoSaved
In-Office
3 Locations
122K-232K Annually
Senior level
122K-232K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software • Semiconductor
The role involves providing technical support for PDKs, digital reference flows, and signoff methodologies, primarily using Cadence tools, while ensuring quality improvements and documentation. The engineer will facilitate ASIC designs, validate processes, and engage with customers for successful tape-outs.
Top Skills: Cadence EdaPerlPythonShell ScriptingTcl
11 Days AgoSaved
Easy Apply
In-Office
Austin, TX, USA
Easy Apply
71K-119K Annually
Junior
71K-119K Annually
Junior
Biotech
As a Design Controls Engineer, you'll design and improve software-focused control systems for regulatory compliance, support software lifecycles, and enhance audit readiness.
Top Skills: PythonSQL
11 Days AgoSaved
In-Office
2 Locations
Mid level
Mid level
Aerospace • Energy
As a Stress and Life Engineer, you will enhance and maintain mechanical analysis software, collaborate on tool integration, engage with engineering teams, and modernize tool architecture for optimal performance within an Agile environment.
Top Skills: Ansys ApdlAnsys WorkbenchC++Fortran
11 Days AgoSaved
In-Office
San Jose, CA, USA
179K-259K Annually
Senior level
179K-259K Annually
Senior level
Artificial Intelligence • Internet of Things • Machine Learning • Semiconductor
Develop and support advanced design automation flows for digital semiconductors, improve EDA tools, and drive process enhancements.
Top Skills: Eda ToolsLinuxPythonShellSpyglassTclUnixVcsXcelium
11 Days AgoSaved
In-Office
Tampa, FL, USA
Expert/Leader
Expert/Leader
Aerospace • Energy • Industrial
The Staff Manufacturing Engineer leads DFM/DFA reviews, collaborates on manufacturability, establishes design standards, mentors junior engineers, and drives continuous improvement in products for U.S. Navy applications.
Top Skills: 3D Cad Software (SolidworksCreoMicrosoft ApplicationsNx Or Similar)
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