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Reposted 12 Days AgoSaved
In-Office
Chandler, AZ, USA
91K-232K Annually
Expert/Leader
91K-232K Annually
Expert/Leader
Hardware • Semiconductor
Lead design of CMOS analog circuits for dsPIC microcontrollers, mentor junior designers, and perform design reviews and silicon validation.
Top Skills: CadenceCmos
Reposted 12 Days AgoSaved
In-Office
3 Locations
136K-265K Annually
Senior level
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Develop physical design methodologies for graphics processors and SOCs, focusing on innovative solutions to PPA problems and ML-based development.
Top Skills: Ml-Based SolutionsStandard Industry Pnr Tools
Reposted 12 Days AgoSaved
In-Office
Rockville, MD, USA
99K-165K Annually
Mid level
99K-165K Annually
Mid level
Greentech • Energy
Responsible for designing and developing mechanical systems, performing process calculations, overseeing system engineering processes, and ensuring compliance with technical specifications and project requirements.
Top Skills: CadMechanical Systems DesignThermal And Hydraulic Systems
Reposted 12 Days AgoSaved
In-Office
Philadelphia, PA, USA
Senior level
Senior level
Design
Responsible for design calculations and technical reports for traction power projects, mentoring junior staff, and ensuring project delivery and compliance with budgets.
Top Skills: Ac Power Distribution SystemsDc Power Distribution SystemsEngineering SoftwareTraction Power Substations
Reposted 12 Days AgoSaved
In-Office
Irvine, CA, USA
127K-187K Annually
Mid level
127K-187K Annually
Mid level
Semiconductor
Design and verify mixed signal circuits such as ADCs, DACs, and PLLs within a team environment, focusing on high-performance transceiver products.
Top Skills: AdcBandgap Bias CircuitsCmosDacFiltersHsimMatlabPllRegulatorsSpectreSpiceVerilog
Reposted 12 Days AgoSaved
In-Office
Westborough, MA, USA
165K-244K Annually
Senior level
165K-244K Annually
Senior level
Semiconductor
The Principal Engineer will lead DFT architecture on multi-die designs, mentor engineers, and implement DFT methodologies for complex ICs.
Top Skills: AsicDftIc DesignPost-Silicon BringupSocStaValidation
Reposted 12 Days AgoSaved
In-Office
Pearland, TX, USA
Senior level
Senior level
Healthtech • Other • Biotech
The Senior QA Design Transfer Engineer participates in design and development activities, ensuring design requirements are met for manufacturing and risk management. They lead analysis meetings, generate engineering change notifications, and mentor teams while ensuring compliance with quality standards.
Top Skills: 21 Cfr 820Iso 13485Iso 14791JmpMinitabOracle
Reposted 12 Days AgoSaved
In-Office
Pearland, TX, USA
Junior
Junior
Healthtech • Other • Biotech
The QA Design Transfer Engineer is responsible for ensuring design outputs are effectively transferred to manufacturing, coordinating risk analysis, and authoring engineering documentation. They also perform root cause analysis and contribute to continuous improvements in product quality and compliance with regulatory standards.
Top Skills: Iso 13485Iso 14971Lean ManufacturingMinitabOracleSix SigmaStatistical Methodologies
12 Days AgoSaved
Easy Apply
In-Office
Emeryville, CA, USA
Easy Apply
170K-220K Annually
Senior level
170K-220K Annually
Senior level
Hardware • Robotics
As a Senior Robotics Engineer, you will ensure the reliability of hardware, debug systems, work in cross-functional teams, and improve robotic operations while diagnosing issues across development cycles.
Top Skills: C/C++DevOpsHardware-In-The-LoopInfrastructure-As-CodePythonVersion Control
Reposted 13 Days AgoSaved
In-Office
4 Locations
83K-122K Annually
Senior level
83K-122K Annually
Senior level
Industrial • Manufacturing
The role involves leading project engineering for material handling systems, collaborating with teams and customers, and ensuring project success.
Top Skills: 3D ModelingPlc ControlsSimulation And Modeling ToolsWcs SoftwareWms
Reposted 13 Days AgoSaved
Easy Apply
In-Office
Rochester, NY, USA
Easy Apply
95K-120K Annually
Senior level
95K-120K Annually
Senior level
Automation • Manufacturing
Lead and manage engineering projects, mentor teams, solve complex design challenges, ensure safety standards, and maintain client relationships.
Top Skills: CfdDeltek VisionFeaMicrosoft ProjectSolidworks
Reposted 13 Days AgoSaved
In-Office
2 Locations
126K-186K Annually
Senior level
126K-186K Annually
Senior level
Semiconductor
This role involves physical design of complex chips, integrating designs across disciplines, mentoring juniors, and scripting for automation.
Top Skills: Cadence InnovusEda ToolsPerlPythonShellTclVerilog
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Reposted 13 Days AgoSaved
In-Office
Chaska, MN, USA
79K-116K Annually
Mid level
79K-116K Annually
Mid level
Healthtech • Manufacturing
The Design Assurance Engineer II will ensure compliance with quality standards, support product development, coordinate risk assessments, and assist in validation processes, while adhering to company values and regulatory requirements.
Top Skills: AnovaDoeFdaGauge R&RIsoMinitabSpc
Reposted 13 Days AgoSaved
In-Office
2 Locations
129K-206K Annually
Senior level
129K-206K Annually
Senior level
Artificial Intelligence • Internet of Things • Machine Learning • Semiconductor
This role involves validating SoC designs through functional logic verification, developing verification plans, analyzing performance, and collaborating with design teams.
Top Skills: C++JavaPerlPythonSystemverilogTclUvm
Reposted 13 Days AgoSaved
Easy Apply
In-Office
Huntsville, AL, USA
Easy Apply
Mid level
Mid level
Aerospace
The Mechanical Engineer II will design and analyze mechanical systems, draft technical drawings, participate in manufacturing, and perform testing and project management tasks.
Top Skills: CadCfdMachining ToolsMaterials ProcessingSoftware Design
Reposted 13 Days AgoSaved
In-Office
San Jose, CA, USA
157K-243K Annually
Senior level
157K-243K Annually
Senior level
Semiconductor
Develop verification infrastructure for AI accelerator IP blocks, create test plans, debug, and mentor junior engineers in a collaborative environment.
Top Skills: C/C++PerlPythonSystem VerilogUvm
Reposted 13 Days AgoSaved
Remote
15 Locations
145K-175K Annually
Senior level
145K-175K Annually
Senior level
Information Technology • Software
As Lead Electrical Engineer, you will oversee project design, construction, and coordination efforts, ensuring compliance with engineering standards and resolving design issues during construction.
Top Skills: Construction ManagementData Center DesignElectrical Engineering
Reposted 13 Days AgoSaved
Easy Apply
In-Office
Casa Grande, AZ, USA
Easy Apply
100K-110K Annually
Mid level
100K-110K Annually
Mid level
Aerospace • Information Technology • Software • Biotech • Design
As a Design and Release Engineer for Airbags, you will research, design, develop, and test airbag systems for vehicles. Responsibilities include analyzing proposals, collaborating with drafters, and maintaining product development history.
Top Skills: Computer Aided Design (Cad)
Reposted 13 Days AgoSaved
In-Office
2 Locations
60K-111K Annually
Mid level
60K-111K Annually
Mid level
Cloud • Hardware • Software • Semiconductor
Cadence is offering a 16-week paid returnship for Physical Design Application Engineers to update skills and re-enter the workforce after caregiving. Candidates will work with EDA tools on Digital Synthesis, Place and Route, and Signoff Analysis.
Top Skills: Digital SynthesisEda ToolsPhysical DesignPlace And RouteSignoff Analysis
Reposted 13 Days AgoSaved
In-Office
San Jose, CA, USA
103K-191K Annually
Senior level
103K-191K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The Lead Applications Engineer will architect memory solutions, provide technical presales support, present IP portfolio to customers, and evaluate performance of memory IP.
Top Skills: AxiDdr4Ddr5DfiFpgaGddr6Hbm2Hbm3Lpddr4Lpddr5MipiRtlSystem VerilogVerilog
Reposted 13 Days AgoSaved
Easy Apply
In-Office
Pittsburgh, PA, USA
Easy Apply
Senior level
Senior level
Fitness
The Lead UI Engineer will develop and maintain UI components, enforce design quality, and collaborate across teams to enhance the design system at Blink Health.
Top Skills: Ai-Assisted ToolsFigmaJavaScriptReactStorybook
Reposted 13 Days AgoSaved
In-Office
4 Locations
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Design Engineer will focus on chip-level physical architecture and integration for ASICs, optimizing die layout and collaborating with cross-functional teams to ensure successful designs meet performance targets.
Top Skills: CadenceLinuxPerlPythonRubyTcl
Reposted 13 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The role involves physical IC design, from RTL to silicon tape-out, including synthesis, verification, timing closure, and collaboration with RTL engineers.
Top Skills: Eda ToolsPerlTcl
Reposted 13 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Design Verification Engineer will develop verification environments using System Verilog and UVM, create verification components, analyze simulation failures, and produce test cases.
Top Skills: C/C++OvmPerlRtlSystem VerilogUvm
Reposted 13 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design interposer layouts for high-speed interfaces while collaborating with cross-functional teams. Requires scripting for automation and expertise in 2.5D/3D designs.
Top Skills: Cadence InnovusCadence IntegrityMentor Graphics CalibrePythonSkillSynopsys 3Dic CompilerTcl
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