Top Design Engineer Jobs

The Bluespec Design Engineer will develop silicon designs using Bluespec and Haskell, focusing on performance and reusable libraries for hardware architecture.

Lead full-cycle PCBA design for spaceflight hardware: requirements, schematic/layout, bring-up, test, verification, and manufacturing handoff. Collaborate with RF, mechanical, software, and FPGA teams, mentor junior engineers, engage CMs/vendors, and drive failure analysis and flight-readiness for high-reliability satellite electronics.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Lead mechanical redesign of UHV and HV semiconductor inspection subsystems from requirements through qualification and manufacturing transfer. Drive architecture, tolerance/GD&T strategy, FEA/thermal/vibration analysis, supplier management, root-cause investigations, and mentor junior engineers to improve performance, reliability, and manufacturability.

Lead system-level design and validation for next-generation optical CD metrology products. Develop physical and computational optical models, define requirements, run prototype experiments, perform trade-off analyses, drive cross-functional troubleshooting, transfer designs to manufacturing, and support customer ramps. Coordinate global teams and may travel up to 25%.

Convert documentation and schematics into assemblies by developing and maintaining manufacturing methods and processes. Support pre-production electronic/electro-mechanical assembly, perform rework and quality testing, estimate manufacturing costs, recommend tooling, and coordinate with development and manufacturing engineering teams.

The Senior Mechanical Design Engineer develops innovative mechanical designs, conducts feasibility studies, and collaborates across disciplines for product lifecycle management.

Design and develop mechanical subsystems for UHV and HV semiconductor inspection modules. Create 3D CAD models, drawings, BOMs; perform tolerance analysis, GD&T, and FEA; support prototyping, supplier development, manufacturing introduction, troubleshooting, and product lifecycle documentation.

Design, simulate, verify, characterize, and validate mixed-signal integrated circuits and semiconductor solutions. Responsibilities include schematic development, circuit modeling, silicon validation, test planning, performance analysis, technical documentation, and cross-functional collaboration with analog, digital, layout, product, test, and applications engineering teams.

Contributes to the design, implementation, simulation, and verification of digital integrated circuits and subsystems. Develops RTL using Verilog or SystemVerilog, supports synthesis, timing analysis, debugging, and performance optimization, and collaborates with architecture, verification, physical design, test, and product engineering teams. Documents specifications, verification plans, and technical results.

Leads the complete hardware design lifecycle for automotive low-voltage zonal ECUs, including requirements, schematics, PCB layout, prototyping, validation, power electronics, signal integrity, EMC, troubleshooting, and production support. Collaborates with cross-functional teams and suppliers to develop robust battery-management and power-distribution hardware. Supports vehicle integration testing and ensures compliance with automotive functional-safety and regulatory standards.

Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.

Staff Design Verification Engineer responsible for planning and executing verification for high-performance out-of-order RISC-V CPU cores, including vector functionality and microarchitectural interactions. Develops verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; leads debug and coverage closure; partners with architecture and design teams; improves verification methodology; and mentors engineers.

Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Own formal verification for high-performance out-of-order CPU core units from planning through signoff. Develop assertions, properties, harnesses, proof infrastructure, and abstraction strategies; analyze counterexamples, vacuity, over-constraints, and proof failures; and verify pipeline control, ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology and automation, and mentor engineers.

Staff Design Verification Engineer responsible for verifying high-performance out-of-order RISC-V CPU core functionality, especially ALU and integer execution pipelines. Owns verification planning, test development, debug, coverage closure, assertions, scoreboards, and signoff from block through core integration. Partners with architecture and RTL teams to identify microarchitectural risks and improve design quality. The role also contributes reusable automation and methodology while mentoring verification engineers.

Own verification of high-performance out-of-order RISC-V CPU cores, with emphasis on vector functionality and microarchitecture. Develop verification plans, environments, checkers, scoreboards, assertions, constrained-random and directed tests, and coverage models. Debug RTL and infrastructure failures, verify RVV behavior and scalar-vector interactions, close coverage gaps, and collaborate with architecture, design, performance, and software teams to achieve signoff quality.

Own formal verification of high-performance out-of-order RISC-V CPU cores from planning through signoff. Develop assertions, properties, checkers, harnesses, abstractions, and proof infrastructure; analyze failures and counterexamples; verify pipeline control, issue and commit logic, load-store ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology, and mentor engineers.

Lead design verification for FPGA/ASIC systems using SystemVerilog/UVM and/or VHDL. Plan and implement constrained-random, metric-driven test plans, build self-checking testbenches and reusable VIP, collect/analyze coverage, mentor engineers, lead DV teams, and drive process improvements for Electronic Warfare systems.

Lead design verification for FPGA/ASIC signal-processing and control systems: plan and build SystemVerilog/UVM/OVM/VHDL self-checking, constrained-random testbenches; develop test plans; collect/analyze coverage; create reusable VIP; lead and mentor DV teams; drive process improvements and execute schedules.

Lead design verification for FPGA signal-processing and control systems: plan and build SystemVerilog/UVM or VHDL self-checking testbenches, create constrained-random metric-driven test plans, collect/analyze coverage, develop reusable VIP, mentor engineers, lead DV teams, and improve verification processes.

Lead and architect FPGA design verification efforts using SystemVerilog/UVM/OVM and VHDL. Develop constrained-random, metric-driven test plans, create reusable VIP, collect/analyze coverage, mentor junior engineers, lead small-to-medium DV teams, and drive process improvements for Electronic Warfare FPGA systems.

Lead verification for a cache-coherent interconnect subsystem based on ARM CHI. Develop verification environments, protocol checkers, scoreboards, assertions, coverage models, and constrained-random tests covering coherency, ordering, flow control, retries, and integration. Analyze failures across specifications, RTL, and testbenches; drive verification strategy, coverage closure, methodology improvements, and durable fixes. Collaborate with architecture, design, formal, and software teams while mentoring engineers and supporting signoff.

Lead the design and development of major aircraft composite structures, including wings, fuselage sections, empennage, and bonded assemblies. Define structural architecture, laminate strategies, joints, load paths, tooling, and assembly approaches. Mentor structures engineers, collaborate with stress and manufacturing teams, and drive designs through PDR, CDR, first article, structural testing, and first flight. The role is hands-on, onsite in Oxnard, California, and requires experience with large-scale aircraft structures and full development cycles.