Jobs at Kandou AI

Coordinate system-level product projects through NPI and pre-production, tracking schedules, milestones, materials, BOMs, risks, NRE, procurement, and budgets. Maintain project documentation, databases, and reports; analyze variances and present status metrics. Collaborate across TPM, engineering, warehouse, shipping, procurement, suppliers, contractors, and management. Support process improvement and standardization while ensuring projects remain within scope, schedule, and budget.

Build and deploy domain-specific AI and agentic tools for semiconductor engineering workflows. Responsibilities include designing reliable agentic systems, integrating LLM tools into analog, digital, and verification environments, creating evaluation pipelines, collaborating with engineering teams, and delivering modular, tested, maintainable code.

Directs silicon characterization strategy and execution across semiconductor product programs, overseeing validation plans, IC bring-up, debug, lab automation, ATE interfacing, evaluation hardware, and reporting. Leads cross-functional teams and external partners, supports customer evaluations and demonstrations, manages equipment and vendor decisions, and drives validation closure and release readiness for SerDes and other high-speed products.

Support advanced R&D efforts designing high-performance digital VLSI systems and control circuitry for high-speed serial links. The intern will use Cadence or Synopsys design flows, organize research findings, assist other digital design activities, and collaborate with mentors and senior leadership. The role is intended for MSc students in electrical or computer engineering and offers hands-on industrial research experience.

Support Advanced R&D by modeling new designs and architectures using signal processing techniques. Organize research findings, assist other business areas with modeling, and contribute to industrial research projects involving analog circuits, communications, DSP, and complex interconnect technologies.

Partners with the CTO to develop next-generation communication and interconnect architectures. Builds models, simulations, and prototypes; explores signaling, coding, equalization, and system-level techniques; evaluates performance, power, latency, area, and manufacturability; and translates theoretical concepts into silicon-ready architectures and intellectual property. Provides technical leadership across research, architecture, and product teams.

Develop and maintain MATLAB, Python, and C++ system-level models for SerDes communication links. Define transceiver block specifications and link budgets with system architects, and support analog, digital, and verification teams. Apply control theory, signal processing, digital communication, signal integrity, circuit simulation, and software engineering practices to semiconductor interconnect design.

Lead firmware development for PCIe and other high-speed server, storage, and networking products. Responsibilities include embedded C/C++ firmware, C-based SDKs, Python automation, SoC and hardware-software interface architecture, build environments, and support for microcontrollers and BMCs. The role collaborates with logic designers on complex SoC products and may involve NVMe, CXL, Ethernet, InfiniBand, simulation platforms, and storage firmware.

Six-month semiconductor engineering internship supporting digital design, verification, physical design, or analog and mixed-signal engineering. Responsibilities may include RTL development, UVM verification, synthesis, floorplanning, place-and-route, static timing analysis, SPICE simulation, and SerDes or PLL design. Candidates will contribute to real semiconductor projects while developing automation and data-analysis scripts.

Lead signal and power integrity analysis and simulation for semiconductor packages, PCBs, channels, connectors, and high-speed interconnects. Develop SI/PI solutions, collaborate with circuit, technology, product, customer, and supplier teams, and resolve system-level design challenges. Evaluate DDR5, PCIe, PAM, and Chord signaling architectures; perform EM modeling, channel extraction, lab validation, and technical communication. The role requires extensive semiconductor industry experience and expertise with Cadence SI/PI tools, Linux-based environments, and scripting.

Leads silicon manufacturing and foundry partner relationships from technology selection through qualification, early volume, and sustaining engineering. Promotes design for manufacture, drives yield, quality, cost, and time-to-market improvements, and coordinates cross-functional semiconductor development activities. Reviews foundry offerings, analyzes production data, conducts supplier audits and business reviews, resolves manufacturing risks, and ensures production requirements and documentation are maintained. The role requires semiconductor process and manufacturing expertise, leadership, analytical skills, and supplier/customer communication.

Lead development, testing, maintenance, and debugging of embedded firmware for silicon products. Design real-time C/C++ applications, integrate hardware peripherals, support silicon design infrastructure, migrate debug software, and implement software validation and verification. Collaborate across platforms including Linux and Windows while using modern CI and development workflows. Optimize low-level code for real-time performance and help drive firmware development independently.

Design and verify high-speed digital circuits for serial transceivers, DDR, and memory interfaces. Responsibilities include RTL design, analog-digital interface specification, synthesis, timing analysis, verification, chip integration, protocol analysis, and post-silicon lab bring-up. The engineer will collaborate with analog, verification, physical implementation, and customer teams while supporting requirements, debugging, characterization, and product delivery.

Develop firmware for new hardware and ASICs, including SoC and board bring-up, bootloaders, platform initialization, peripheral integration, and hardware debugging. Collaborate with architecture, design, verification, validation, and application teams to resolve hardware-firmware issues. Use C/C++, Linux, RTOS platforms, PCIe/CXL, OpenBMC, scripting, CI workflows, testing, code reviews, and documentation.

Conduct research on simultaneous bidirectional communication over wideband copper serial links. Develop behavioral models of copper channels and transceiver architectures, investigate analog and digital self-interference cancellation, evaluate channel impairments and non-idealities, and simulate communication building blocks using Python or circuit-level CAD tools. Assess data rates, energy efficiency, and implementation complexity, then present findings in a technical report and oral presentation.

Develop and debug embedded firmware for RTOS and Linux-based systems. Responsibilities include RTOS porting, SoC and board bring-up, bootloader and platform initialization, peripheral integration, hardware-firmware troubleshooting, architecture and coding, validation, code reviews, unit testing, documentation, and CI automation. The role requires C/C++ expertise, CPU and memory architecture knowledge, Linux kernel and driver familiarity, hardware debugging, and collaboration across hardware, validation, and application teams.

Develop Linux software for Kandou’s AI hardware products, including kernel and device drivers, embedded software, hardware bring-up, and hardware/software integration. Work with PCIe, I3C, SPI, JTAG, CXL, NVMe, and AXI architectures across x86 and ARM systems. Define interfaces, contribute to storage, networking, or accelerated-computing systems, and use modern development, CI/CD, quality assurance, and test-automation practices.

Lead digital physical design for semiconductor and chiplet-based AI infrastructure products. Responsibilities include RTL-to-GDS implementation, synthesis, floor planning, place and route, clock tree synthesis, timing closure, STA, power and signal integrity analysis, physical verification, formal equivalence checking, DFT implementation, flow development, IP and chip integration, tapeout, release management, and customer IP delivery.

Leads custom analog layout and verification for high-speed SerDes and memory I/O circuits in advanced semiconductor nodes. Collaborates with design teams on circuit implementation, supports IP and chip-level integration, assists with customer requirements and IP delivery, and applies high-speed layout techniques involving matching, parasitic minimization, power grids, ESD, EM, and IR-drop analysis.

Plan production against customer demand, capacity, inventory, and delivery targets. Maintain master schedules, prepare manufacturing purchase orders, coordinate supply chain partners, track operational metrics, manage WIP reconciliation, support forecasting and Sales and Operations Planning, and identify delivery risks. The role also supports new production introduction, invoice reconciliation, customer order commitments, and recovery planning in a high-volume semiconductor or electronics manufacturing environment.