Jobs at Kandou AI

Architects Kandou’s customer-facing Randa platform, including SDKs, APIs, diagnostics, telemetry, integrations, and developer documentation. Leads interoperability qualification across networking, switching, and BMC platforms; owns compatibility, release governance, regression strategy, and customer-specific adaptation layers. Partners with firmware, validation, product, and field engineering teams to deliver secure, backward-compatible releases and represents software capabilities in customer technical discussions and escalations.

Leads hands-on development and delivery of real-time embedded firmware modules for heterogeneous SoCs. Responsibilities include C/C++ coding, RTOS integration, low-level drivers, bootloaders, secure boot, firmware updates, hardware bring-up, debugging, validation, code reviews, planning, documentation, cross-functional integration, and mentoring. The role emphasizes RISC-V platforms, peripheral interfaces, silicon development tools, and ownership from requirements through release.

Lead characterization of retimer silicon and active electrical cable channels from measurement planning through datasheet-limit derivation and validation handoff. Characterize high-speed SerDes performance across process, voltage, temperature, channel, power, and thermal conditions. Own 50 GHz-plus VNA measurements, mixed-mode analysis, statistical guard-band development, equipment coordination, and technical reviews. Establish defensible channel classes, limits, and qualification thresholds for manufacturing and customer specifications.

Leads hands-on development and delivery of real-time embedded firmware for high-speed AEC retimer silicon. Responsibilities include C/C++ coding, state machines, drivers, SerDes adaptation, hardware and silicon bring-up, debugging, testing, CI, and cross-functional coordination. The role mentors engineers, establishes coding standards, manages work packages, and supports pre-silicon through production development across RISC-V or ARM platforms.

Leads electrical and mechanical optimization of high-speed connectors, cable assemblies, and cable-to-PCB interfaces. Defines interconnect architectures, develops HFSS electromagnetic models, plans Proof-of-Life studies, and validates designs through VNA, TDR, and oscilloscope measurements. Collaborates with signal integrity, mechanical, systems, manufacturing, suppliers, and customers to deliver manufacturable solutions. Provides technical recommendations, manages development programs, mentors engineers, and supports design reviews, qualifications, and customer engagements.

Supports multi-entity and multi-currency accounting across global operations, including vendor payments, journal entries, AP/AR, reconciliations, month-end close, audit documentation, and finance administration. The role also supports AI implementation in finance operations and offers mentorship for a recent graduate building foundational accounting expertise.

Develop firmware modules and services for memory fabric products, implementing differentiating product features on embedded microcontrollers and processors. Design and develop PCIe, CXL, and NVMe firmware using C or C++, including C-based SDKs. Enable RTOS and Zephyr OS platforms, integrate SoC interfaces including PCIe, NVMe, DDR, AMBA, and AHB, and collaborate with architecture, development, QA, product, and customer teams. Preferred experience includes storage or SSD firmware, flash management, and Renode or QEMU-based development.

Architect and lead CMIS software stacks, host interoperability testing, manufacturing test orchestration, telemetry pipelines, customer SDKs, and developer tools. Ensure compliance with CMIS, OSFP, SFF-8024, OIF, and related standards. Responsibilities include regression testing with hyperscalers, ATE integration, yield analytics, firmware-to-cloud telemetry, release management, architecture documentation, and customer, manufacturing, and standards engagement. Travel up to 25% is required.

Designs and validates analog circuit models across abstraction levels, from mathematical descriptions to post-layout performance. Generates sub-block specifications from architecture and system models, verifies modeled performance, automates simulations, documents methodologies, presents results, and collaborates with design and systems teams to optimize circuit and system specifications.

Own block-level physical implementation for advanced FinFET semiconductor designs, including synthesis, SDC constraints, floorplanning, placement, clock-tree synthesis, routing, MCMM timing closure, ECOs, and physical verification sign-off. Collaborate with digital design teams to resolve implementation bottlenecks, automate flows with Tcl and Python, and prepare tape-out documentation. The role requires advanced-node tape-out experience, low-power implementation expertise, and proficiency with industry-standard EDA tools.

Designs, prototypes, validates, and supports FPGA architectures throughout the project lifecycle. Collaborates with architecture, system software, and IP provider teams; independently owns FPGA projects; develops RTL; integrates AXI/AMBA-connected logic blocks; and performs lab bring-up and validation. The role requires shipping FPGA designs involving compute, networking, storage, or processor-prototyping applications, with preferred expertise in PCIe and embedded processor datapaths.

Architect and develop embedded firmware for memory fabric products based on CXL and PCIe. Lead firmware implementation for SoC and silicon products, including bare-metal and RTOS environments, Zephyr OS, NVMe, DDR, AMBA/AHB, and on-chip memory interfaces. Collaborate with architecture, engineering, QA, product, and customer teams across sites. Mentor team members and support simulation or virtual-platform development.

Develop embedded firmware modules and services for memory fabric products with DDR interfaces. Design bare-metal and RTOS/Zephyr firmware for DDR memory controllers, PCIe, NVMe, and SoC interfaces using C or C++. Collaborate with architecture, development, QA, validation, product management, and customer teams. Preferred experience includes storage or SSD firmware, CXL, flash management, and simulation or virtual platform development.

Coordinate system-level product projects through NPI and pre-production, tracking schedules, milestones, materials, BOMs, risks, NRE, procurement, and budgets. Maintain project documentation, databases, and reports; analyze variances and present status metrics. Collaborate across TPM, engineering, warehouse, shipping, procurement, suppliers, contractors, and management. Support process improvement and standardization while ensuring projects remain within scope, schedule, and budget.

Build and deploy domain-specific AI and agentic tools for semiconductor engineering workflows. Responsibilities include designing reliable agentic systems, integrating LLM tools into analog, digital, and verification environments, creating evaluation pipelines, collaborating with engineering teams, and delivering modular, tested, maintainable code.

Directs silicon characterization strategy and execution across semiconductor product programs, overseeing validation plans, IC bring-up, debug, lab automation, ATE interfacing, evaluation hardware, and reporting. Leads cross-functional teams and external partners, supports customer evaluations and demonstrations, manages equipment and vendor decisions, and drives validation closure and release readiness for SerDes and other high-speed products.

Support advanced R&D efforts designing high-performance digital VLSI systems and control circuitry for high-speed serial links. The intern will use Cadence or Synopsys design flows, organize research findings, assist other digital design activities, and collaborate with mentors and senior leadership. The role is intended for MSc students in electrical or computer engineering and offers hands-on industrial research experience.

Support Advanced R&D by modeling new designs and architectures using signal processing techniques. Organize research findings, assist other business areas with modeling, and contribute to industrial research projects involving analog circuits, communications, DSP, and complex interconnect technologies.

Partners with the CTO to develop next-generation communication and interconnect architectures. Builds models, simulations, and prototypes; explores signaling, coding, equalization, and system-level techniques; evaluates performance, power, latency, area, and manufacturability; and translates theoretical concepts into silicon-ready architectures and intellectual property. Provides technical leadership across research, architecture, and product teams.

Develop and maintain MATLAB, Python, and C++ system-level models for SerDes communication links. Define transceiver block specifications and link budgets with system architects, and support analog, digital, and verification teams. Apply control theory, signal processing, digital communication, signal integrity, circuit simulation, and software engineering practices to semiconductor interconnect design.