Jobs at Kandou AI

Develop firmware modules and services for memory fabric products, implementing differentiating product features on embedded microcontrollers and processors. Design and develop PCIe, CXL, and NVMe firmware using C or C++, including C-based SDKs. Enable RTOS and Zephyr OS platforms, integrate SoC interfaces including PCIe, NVMe, DDR, AMBA, and AHB, and collaborate with architecture, development, QA, product, and customer teams. Preferred experience includes storage or SSD firmware, flash management, and Renode or QEMU-based development.

Architect and lead CMIS software stacks, host interoperability testing, manufacturing test orchestration, telemetry pipelines, customer SDKs, and developer tools. Ensure compliance with CMIS, OSFP, SFF-8024, OIF, and related standards. Responsibilities include regression testing with hyperscalers, ATE integration, yield analytics, firmware-to-cloud telemetry, release management, architecture documentation, and customer, manufacturing, and standards engagement. Travel up to 25% is required.

Designs and validates analog circuit models across abstraction levels, from mathematical descriptions to post-layout performance. Generates sub-block specifications from architecture and system models, verifies modeled performance, automates simulations, documents methodologies, presents results, and collaborates with design and systems teams to optimize circuit and system specifications.

Own block-level physical implementation for advanced FinFET semiconductor designs, including synthesis, SDC constraints, floorplanning, placement, clock-tree synthesis, routing, MCMM timing closure, ECOs, and physical verification sign-off. Collaborate with digital design teams to resolve implementation bottlenecks, automate flows with Tcl and Python, and prepare tape-out documentation. The role requires advanced-node tape-out experience, low-power implementation expertise, and proficiency with industry-standard EDA tools.

Designs, prototypes, validates, and supports FPGA architectures throughout the project lifecycle. Collaborates with architecture, system software, and IP provider teams; independently owns FPGA projects; develops RTL; integrates AXI/AMBA-connected logic blocks; and performs lab bring-up and validation. The role requires shipping FPGA designs involving compute, networking, storage, or processor-prototyping applications, with preferred expertise in PCIe and embedded processor datapaths.

Architect and develop embedded firmware for memory fabric products based on CXL and PCIe. Lead firmware implementation for SoC and silicon products, including bare-metal and RTOS environments, Zephyr OS, NVMe, DDR, AMBA/AHB, and on-chip memory interfaces. Collaborate with architecture, engineering, QA, product, and customer teams across sites. Mentor team members and support simulation or virtual-platform development.

Develop embedded firmware modules and services for memory fabric products with DDR interfaces. Design bare-metal and RTOS/Zephyr firmware for DDR memory controllers, PCIe, NVMe, and SoC interfaces using C or C++. Collaborate with architecture, development, QA, validation, product management, and customer teams. Preferred experience includes storage or SSD firmware, CXL, flash management, and simulation or virtual platform development.

Coordinate system-level product projects through NPI and pre-production, tracking schedules, milestones, materials, BOMs, risks, NRE, procurement, and budgets. Maintain project documentation, databases, and reports; analyze variances and present status metrics. Collaborate across TPM, engineering, warehouse, shipping, procurement, suppliers, contractors, and management. Support process improvement and standardization while ensuring projects remain within scope, schedule, and budget.

Build and deploy domain-specific AI and agentic tools for semiconductor engineering workflows. Responsibilities include designing reliable agentic systems, integrating LLM tools into analog, digital, and verification environments, creating evaluation pipelines, collaborating with engineering teams, and delivering modular, tested, maintainable code.

Directs silicon characterization strategy and execution across semiconductor product programs, overseeing validation plans, IC bring-up, debug, lab automation, ATE interfacing, evaluation hardware, and reporting. Leads cross-functional teams and external partners, supports customer evaluations and demonstrations, manages equipment and vendor decisions, and drives validation closure and release readiness for SerDes and other high-speed products.

Support advanced R&D efforts designing high-performance digital VLSI systems and control circuitry for high-speed serial links. The intern will use Cadence or Synopsys design flows, organize research findings, assist other digital design activities, and collaborate with mentors and senior leadership. The role is intended for MSc students in electrical or computer engineering and offers hands-on industrial research experience.

Support Advanced R&D by modeling new designs and architectures using signal processing techniques. Organize research findings, assist other business areas with modeling, and contribute to industrial research projects involving analog circuits, communications, DSP, and complex interconnect technologies.

Partners with the CTO to develop next-generation communication and interconnect architectures. Builds models, simulations, and prototypes; explores signaling, coding, equalization, and system-level techniques; evaluates performance, power, latency, area, and manufacturability; and translates theoretical concepts into silicon-ready architectures and intellectual property. Provides technical leadership across research, architecture, and product teams.

Develop and maintain MATLAB, Python, and C++ system-level models for SerDes communication links. Define transceiver block specifications and link budgets with system architects, and support analog, digital, and verification teams. Apply control theory, signal processing, digital communication, signal integrity, circuit simulation, and software engineering practices to semiconductor interconnect design.

Six-month semiconductor engineering internship supporting digital design, verification, physical design, or analog and mixed-signal engineering. Responsibilities may include RTL development, UVM verification, synthesis, floorplanning, place-and-route, static timing analysis, SPICE simulation, and SerDes or PLL design. Candidates will contribute to real semiconductor projects while developing automation and data-analysis scripts.

Leads silicon manufacturing and foundry partner relationships from technology selection through qualification, early volume, and sustaining engineering. Promotes design for manufacture, drives yield, quality, cost, and time-to-market improvements, and coordinates cross-functional semiconductor development activities. Reviews foundry offerings, analyzes production data, conducts supplier audits and business reviews, resolves manufacturing risks, and ensures production requirements and documentation are maintained. The role requires semiconductor process and manufacturing expertise, leadership, analytical skills, and supplier/customer communication.

Design and verify high-speed digital circuits for serial transceivers, DDR, and memory interfaces. Responsibilities include RTL design, analog-digital interface specification, synthesis, timing analysis, verification, chip integration, protocol analysis, and post-silicon lab bring-up. The engineer will collaborate with analog, verification, physical implementation, and customer teams while supporting requirements, debugging, characterization, and product delivery.

Conduct research on simultaneous bidirectional communication over wideband copper serial links. Develop behavioral models of copper channels and transceiver architectures, investigate analog and digital self-interference cancellation, evaluate channel impairments and non-idealities, and simulate communication building blocks using Python or circuit-level CAD tools. Assess data rates, energy efficiency, and implementation complexity, then present findings in a technical report and oral presentation.

Develop and debug embedded firmware for RTOS and Linux-based systems. Responsibilities include RTOS porting, SoC and board bring-up, bootloader and platform initialization, peripheral integration, hardware-firmware troubleshooting, architecture and coding, validation, code reviews, unit testing, documentation, and CI automation. The role requires C/C++ expertise, CPU and memory architecture knowledge, Linux kernel and driver familiarity, hardware debugging, and collaboration across hardware, validation, and application teams.

Lead digital physical design for semiconductor and chiplet-based AI infrastructure products. Responsibilities include RTL-to-GDS implementation, synthesis, floor planning, place and route, clock tree synthesis, timing closure, STA, power and signal integrity analysis, physical verification, formal equivalence checking, DFT implementation, flow development, IP and chip integration, tapeout, release management, and customer IP delivery.