Teams at Kandou AI

Partners with the CTO to develop next-generation communication and interconnect architectures. Builds models, simulations, and prototypes; explores signaling, coding, equalization, and system-level techniques; evaluates performance, power, latency, area, and manufacturability; and translates theoretical concepts into silicon-ready architectures and intellectual property. Provides technical leadership across research, architecture, and product teams.

Develop and maintain MATLAB, Python, and C++ system-level models for SerDes communication links. Define transceiver block specifications and link budgets with system architects, and support analog, digital, and verification teams. Apply control theory, signal processing, digital communication, signal integrity, circuit simulation, and software engineering practices to semiconductor interconnect design.

Lead firmware development for PCIe and other high-speed server, storage, and networking products. Responsibilities include embedded C/C++ firmware, C-based SDKs, Python automation, SoC and hardware-software interface architecture, build environments, and support for microcontrollers and BMCs. The role collaborates with logic designers on complex SoC products and may involve NVMe, CXL, Ethernet, InfiniBand, simulation platforms, and storage firmware.