Search the 24 jobs at Astera Labs

The Firmware Engineer is responsible for architecting and developing firmware and microcontroller subsystems for Astera Labs' SoC and systems products, ensuring the firmware meets customer needs and implements key product features. The role includes debugging and developing complex systems while working in a team environment.

The Principal Formal Verification Engineer will develop detailed test plans for formal verification, identify key components for design correctness, implement verification models, and collaborate with design teams to enhance product design quality and performance. They will also need to streamline verification processes and assist with the implementation of assertions.

The Senior Formal Verification Engineer will be responsible for developing and implementing formal verification abstractions, models, and assertions to identify critical logic components and ensure design correctness. The role involves collaborating with designers, performing assertion-based model checking, and participating in design reviews to enhance performance and design interfaces.

Regional Sales Executive responsible for developing account strategies and engaging with leading cloud service providers, server and networking OEMs to design in Astera Labs' portfolio of connectivity products. Key responsibilities include developing a regional sales plan, driving sales efforts, fostering strong customer relationships, and partnering with industry companies. Requires a minimum of 5 years' experience selling complex SoC/silicon products.

As a Senior Field Applications Engineer at Astera Labs, you will work with leading cloud service providers and server OEMs to design solutions using Astera Labs' connectivity products. Your responsibilities include understanding customer requirements, proposing solutions, and providing design-in support. This role requires hands-on experience with high-speed protocols, board design techniques, and memory technologies.

The Sr. Principal Technologist at Astera Labs drives the architecture and definition of high-speed connectivity products while engaging with clients to solve challenges in hyperscale data centers. The role emphasizes expertise in system and SOC architecture, along with PCIe and CXL technologies, to innovate and optimize solutions.

Provide technical guidance to customers, generate collateral for existing and new products, and drive innovation by providing feedback to internal teams. Requires experience with PCIe/CXL and designing complex SoC/silicon products.

The Senior Product Applications Engineering Manager will lead a team providing technical support for semiconductor products, address customer design challenges, generate product collateral, and collaborate with internal teams for product innovation. This role requires managing customer relationships and hands-on lab work to troubleshoot high-speed interface issues.

As a Senior Software/Firmware Engineer at Astera Labs, you will architect and develop firmware and microcontroller subsystems for SoC and systems products, ensuring the integration of differentiated features and customer interaction. You should have a strong technical background in embedded software, firmware development, and relevant communication protocols, focusing on the needs of the customer while coordinating with hardware teams.

As a Senior Field Applications Engineer, you will lead a team to act as trusted technical advisors for cloud service providers. Your role involves designing solutions using Astera Labs’ connectivity products, proposing solutions based on customer needs, and collaborating with engineering to drive product innovation.

Seeking a Senior Digital Design Engineer to design and implement high-performance digital solutions, focusing on RTL development and synthesis, collaborating on PCIe/CXL protocols, and ensuring timing closure and verification completeness.

The Senior Digital Design Engineer will design and implement high-performance digital solutions, focusing on RTL development and synthesis. Responsibilities include collaborating on IP integration, overseeing designs from architecture to GDS, ensuring timing closure, and debugging pre- and post-silicon. The role requires expertise in various design tools and methodologies, along with hands-on processor experience.

The Principal Digital Design Engineer will design and implement high-performance digital solutions, focusing on RTL development, IP integration, and timing closure. Responsibilities include ownership of block-level and full-chip designs, ensuring verification completeness, and managing pre-and post-silicon debug processes.

The Principal Digital Design Engineer will design and implement high-performance digital solutions focusing on RTL development and synthesis. Responsibilities include collaborating on IP integration for PCIe/CXL protocols, ensuring timing closure, and overseeing the pre- and post-silicon debug process.

The Design Verification Engineer will develop and execute verification plans, write and execute test sequences, collaborate with RTL designers to debug issues, and utilize coding expertise for functional verification on PCIe and CXL protocols.

The Senior Physical Design Engineer will develop and support complex SoC/silicon products for various applications. Responsibilities include using physical design tools, driving designs from architecture to production, collaborating with IP vendors, and ensuring timing closure and formal verification.

As a Senior DFT Engineer at Astera Labs, you will work on developing next-generation connectivity products, engaging in all product lifecycle stages. Collaboration with various teams is essential, focusing on chip design and DFT techniques such as ATPG and JTAG while ensuring quality through testing and analysis.

As a Principal DFT Engineer at Astera Labs, you will lead the development of connectivity products, ensuring quality from design to production. This includes collaboration with multiple engineering teams on validation, testing, and analysis of semiconductor solutions.

The Senior Design Verification Engineer will develop and execute verification plans, write and execute test sequences, collaborate with RTL designers, and analyze coverage data. Responsibilities include using coding expertise for functional verification and creating VIP abstraction layers for simplified verification processes.

As a Principal Physical Design Engineer, you will lead complex SoC/silicon product designs for Server, Storage, and Networking applications. You will be responsible for full chip or block level ownership, synthesis, timing closure, and verification, while utilizing backend tools and methodologies.