Jobs at Astera Labs

Support layout design of analog and mixed-signal blocks, perform LVS/DRC/PEX verification, assist floorplanning, placement, routing and matching, optimize layouts with circuit designers for performance and manufacturability, and document work for reviews and tape-out under mentorship.

Lead block- and top-level physical implementation for high-speed transceiver IPs: floorplanning, placement, CTS, routing, routing signoff, EM/IR and congestion analysis, timing closure, IP integration, ECO/tapeout support, and automation scripting to optimize area, power, and timing in advanced process nodes.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.

Develop, optimize, and maintain embedded firmware for optical engines and photonic integrated circuits, including control and calibration of optical modules and high-speed link optimization.

Lead customer-facing technical engagements for optical connectivity, driving solution adoption, link bring-up, debug, and system validation. Partner with silicon, firmware, hardware, and optical module partners to develop test methodologies, documentation, and field enablement while mentoring engineers and representing the company at industry forums.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead RTL design and implementation for connectivity silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure, CDC, lint, and low-power goals. Mentor engineers, debug pre- and post-silicon issues, and drive methodology for timely tapeouts.

Lead architecture and hands-on design of high-speed analog/mixed-signal blocks (SerDes, PLLs, ADC/DACs, references). Define specifications, run PVT/Monte Carlo simulations, drive layout and floorplanning, lead silicon bring-up and characterization, and mentor engineers while collaborating with digital, system, product, and packaging teams.

Lead end-to-end program planning and execution for AMS IP development from specification through tape-out and silicon bring-up. Orchestrate cross-functional teams (circuit design, layout, verification, validation), manage schedules, risks, budgets, and vendor/foundry coordination, and drive process improvements and stakeholder alignment to deliver high-quality silicon on schedule.

Lead advanced packaging R&D for photonics products, defining process flows (wafer/panel/die), integrating EIC-to-PIC, qualifying materials and equipment, partnering with OSATs and vendors, and driving yield, reliability, PDKs, and packaging design rules for NPO/CPO products.

Lead strategic China customer programs and act as senior cross-functional bridge to HQ. Drive integrated program plans, manage schedules, risks, escalations, and executive communications to ensure product readiness, production ramps, and long-term account success. Build scalable China support model, governance, and operating cadence while improving processes and cross-functional handoffs.

Lead formal verification for complex IP and SoC designs: create formal plans, develop assertions and properties, drive proof convergence, deploy verification flows and tools, mentor engineers, triage bugs, and support verification sign-off to ensure first-pass silicon success.

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.

The Senior Principal Engineering Program Manager will lead ASIC product development, ensuring timely execution, risk management, and cross-functional alignment across various teams to deliver revenue-critical silicon solutions.

The Senior Principal Technologist will drive the architecture and development of data center memory solutions, engage with customers, and influence product features using expertise in system and memory architecture and technologies.

Lead architecture and RTL development for high-speed Ethernet and AI scale-up connectivity ASICs. Define microarchitecture, packet processing, DMA/RDMA acceleration, QoS, congestion management, and hardware/software interfaces. Drive designs from architecture through RTL, verification, tapeout, and post-silicon bring-up while mentoring senior engineers and aligning cross-functional teams to performance, power, and manufacturability targets.

Senior technical leader defining ASIC architecture and driving RTL design, verification, tapeout, and post-silicon bring-up for high-performance Ethernet and AI connectivity products. Lead microarchitecture for MACs, NIC datapaths, packet processing, DMA, RDMA/transport acceleration, congestion control, virtualization, and hardware/software interfaces while mentoring teams and meeting performance, power, area, and reliability targets.

The Senior Product Engineer will lead high-speed semiconductor product development, overseeing validation, testing, and ATE programming, while ensuring quality delivery to customers.

Lead product management for Smart Cable Modules, defining product strategy, engaging customers, and ensuring products meet AI infrastructure needs.

Lead the functional verification of advanced ASICs, overseeing test planning, execution, and coverage analysis, while collaborating with various teams.