Jobs at Astera Labs

The Senior VLSI Design Engineer will design and implement digital blocks for complex semiconductor chips, tackling logic challenges and ensuring robust performance in AI infrastructure solutions.

As a Senior Physical Design Engineer, you will oversee the physical implementation of complex semiconductor designs and guarantee their performance and integrity.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.

The job involves defining product requirements, engaging with customers, and collaborating with teams to deliver semiconductor products for AI infrastructure.

The Senior Emulation Engineer will execute emulation flows, debug and validate semiconductor chips, and collaborate with cross-functional teams to enhance hardware-software integration.

The Principal Product Applications Engineer at Astera Labs provides technical guidance to ODMs, supports semiconductor product design, addresses challenges, and improves processes.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Responsible for full verification lifecycle of complex ASICs, from planning to debugging coverage measures. Collaborate with design teams and develop test plans.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

Build and operate ML infrastructure for LLMs and agent systems: model gateways, routing, serving, telemetry, observability, evaluation, cost-aware routing, dashboards, and APIs/SDKs to enable reliable production AI at scale.

The Principal Product Applications Engineer will engage with customers, support PCIe product adoption, troubleshoot system issues, and create technical documentation while collaborating with cross-functional teams.

The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.

The Lead ATE Test Engineer develops and oversees SoC test strategies, collaborates with teams, defines ATE programs, and ensures high-quality product transition to manufacturing.

Develop, optimize, and maintain embedded firmware for optical engines and photonic integrated circuits, including control and calibration of optical modules and high-speed link optimization.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead customer-facing technical engagements for optical connectivity, driving solution adoption, link bring-up, debug, and system validation. Partner with silicon, firmware, hardware, and optical module partners to develop test methodologies, documentation, and field enablement while mentoring engineers and representing the company at industry forums.