Jobs at Astera Labs

Leads hardware NPI programs from design release through validation, manufacturing readiness, customer preparation, and launch. Owns integrated schedules, budgets, dependencies, risks, readiness reviews, and cross-functional execution across engineering, manufacturing, supply chain, quality, finance, operations, customers, and suppliers. Drives PCB/PCBA builds, supplier and contract manufacturer coordination, issue resolution, dashboards, process improvements, workflow automation, and executive communication. Coaches teams and supports predictable delivery of AI infrastructure connectivity hardware.

Develop front-end digital designs for high-performance network controllers, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Own complex SoC and ASIC designs from architecture through GDS and production while supporting high-speed protocols such as PCIe, UALink, and Ethernet. Collaborate with customers and internal teams, debug silicon, and use Synopsys or Cadence design flows.

Lead architecture and production delivery of embedded firmware and software for Ethernet retimers and high-speed connectivity platforms. Own hardware abstraction, drivers, calibration, link management, diagnostics, telemetry, validation, and customer deployment. Debug PHY, SERDES, FEC/PCS, MAC, and retimer interactions using lab measurements and automation. Provide technical leadership across silicon, analog, systems, validation, and applications teams while mentoring engineers and supporting customer bring-up.

Lead end-to-end test engineering for mixed-signal silicon and high-speed connectivity products, from product definition through high-volume manufacturing. Define test strategies, architect and validate tester hardware, optimize coverage, yield, cost, and test time, and resolve complex failures using lab and manufacturing data. Partner across design, DFT, product engineering, operations, quality, and manufacturing while mentoring engineers and guiding technical decisions.

Design, develop, and deploy LLM-powered agentic applications for RTL, physical and analog design, linting, static analysis, and formal verification. Build engineering assistants, dialogue systems, retrieval infrastructure, databases, and dashboards integrated with CAD/EDA workflows. Collaborate with hardware design, design verification, formal verification, and CAD teams to identify challenges and deliver AI-assisted tools. Apply software engineering and AI/ML expertise to accelerate debugging, coverage closure, lint analysis, RTL optimization, and formal proof convergence.

Develop proactive executive talent strategies for Astera Labs by partnering with senior leaders, analyzing semiconductor and silicon talent markets, building executive pipelines, and leading searches from strategy through close. The role advises VP, C-suite, and board-level stakeholders on organizational needs, leadership profiles, assessment criteria, succession planning, and future hiring priorities. This is a fully in-person position in San Jose.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.

Lead front-end digital design for high-performance switch ASICs, translating microarchitecture into RTL and owning blocks through synthesis, timing closure, verification, DFT, physical implementation, and GDS delivery. Partner with cross-functional teams on high-speed connectivity protocols, silicon bring-up, lab debugging, and root-cause analysis. Provide technical leadership across complex SoC projects supporting AI infrastructure, networking, server, and storage applications.

Own full-chip and block-level physical design for complex SoC and silicon products from architecture through GDSII and production. Responsibilities include synthesis, place and route, clock tree synthesis, timing closure, formal equivalence, physical verification, DFT, ECOs, IP vendor collaboration, and backend tool flow development for advanced process technologies. The role requires driving multiple complex designs, supporting customer engagements, and working independently in a fast-paced environment.

Lead microarchitecture and RTL development for complex connectivity IPs and subsystems. Translate system requirements into high-performance hardware designs, optimize latency, area, and power, and address flow control, buffering, arbitration, and error handling. Collaborate with verification, SoC integration, and physical design teams; support silicon bring-up and post-silicon debugging. Provide technical leadership through reviews, architecture ownership, and mentoring.

Lead end-to-end solution architecture for Oracle Cloud Fusion Financials, including financial modules, integrations, data flows, governance, controls, reporting integrity, and ERP modernization. Partner with Finance, Enterprise Architecture, and implementation teams to support global financial operations, regulatory compliance, implementations, upgrades, and complex system challenges.

Leads functional verification for advanced ASICs and SoCs across planning, test development, simulation, emulation, debugging, coverage analysis, and closure. Develops directed and constrained-random SystemVerilog/UVM tests, collaborates with software, systems, and RTL teams, and drives verification methodologies for server and networking applications. The role also addresses switching architectures, packet processing, PCIe, Ethernet, NoC, and hardware-software co-verification.

Provides technical guidance to ODMs developing semiconductor products, especially PCIe and CXL solutions. Responsibilities include customer-system bring-up and debugging, resolving complex silicon, firmware, hardware, and system issues, directing internal teams, creating technical documentation, supporting compliance testing, and engaging global customers onsite. The role also requires extensive lab work with high-speed test equipment and collaboration with sales, FAE, and engineering teams.

Lead full-custom analog and mixed-signal layout for high-speed SerDes transceiver IPs in advanced FinFET processes. Responsibilities include floorplanning, layout integration, parasitic minimization, matching, shielding, DRC/LVS/ERC and EM/IR signoff, post-layout simulation support, analog-digital integration, debugging, and tapeout release.

Lead design verification for complex ASIC and SoC connectivity silicon. Develop verification plans, UVM-based SystemVerilog testbenches, assertions, scoreboards, coverage models, and regression automation. Verify PCIe, UALink, and UCIe switching behavior through directed and constrained-random testing. Debug simulation failures, close functional and code coverage, support issue isolation and silicon bring-up, and communicate verification status, risks, and recommendations to technical stakeholders.

Develops front-end digital circuit designs for high-performance network controllers, including microarchitecture, RTL, simulation, synthesis, IP integration, verification, DFT, silicon bring-up, and debugging. The role involves working with high-speed protocols such as PCIe, UALink, Esun, and Ethernet, using Synopsys or Cadence design flows and UVM-based verification. A Bachelor’s degree in Electrical Engineering and US work authorization are required.

Develop and execute verification strategies for connectivity ASICs and SoCs supporting PCIe, UALink, and UCI protocols. Build UVM-based SystemVerilog testbenches, test scenarios, assertions, scoreboards, and coverage models. Debug simulation failures, drive functional and code coverage closure, automate regressions, and collaborate with architecture, RTL, firmware, design, and post-silicon teams on root-cause analysis and silicon readiness.

Develop front-end digital designs for high-performance network controllers, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and GDS ownership. The role requires expertise in PCIe, UALink, ESUN, and Ethernet protocols, Synopsys or Cadence design flows, UVM verification, silicon bring-up, and small-geometry CMOS. Candidates will support complex networking or server/storage SoC products and collaborate with customers and cross-functional teams.

Leads high-priority cross-functional business and technical programs across strategic sales opportunities, product development, semiconductor supply chains, and AI infrastructure initiatives. Establishes accountability, tracks risks and dependencies, drives issue resolution, prepares executive reporting, and develops customer and market intelligence. Partners with senior leadership, Sales, Product, Engineering, FAE, Operations, and Supply Chain teams to accelerate growth and improve execution.

Supports G&A and engineering leaders as an HR advisor, coach, and partner. Responsibilities include employee relations, workplace investigations, employment-law compliance, performance management, talent reviews, organizational design, workforce planning, compensation support, and manager development. The role partners with HR Operations, Legal, Compensation, and Centers of Excellence to scale effective people practices and address talent, retention, and engagement needs.