Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.

The Senior Firmware Verification Engineer will verify firmware for SoC products, develop test plans, review code, and ensure quality through testing methodologies.

Seeking a Sr. Principal Technologist to drive architecture for AI software solutions, influencing products and managing customer engagements in hyperscale data centers.

Seeking a Lead Software QA Engineer to design and execute functional, performance, and interoperability tests for PCIe switch technology, collaborating with multiple teams and mentoring others.

The Principal Firmware Engineer will architect and develop firmware for SoC products, focusing on complex silicon solutions for server, storage, and networking applications.

The Principal Product Manager will define product requirements, lead customer engagements, and support market strategies for the Taurus Ethernet Retimer portfolio, driving product success in silicon hardware and software solutions.

The Senior Digital Design Engineer will focus on front-end design and development of digital IP blocks, including RTL design, verification, and integration within ASIC systems, with a focus on high-performance standards.

The Principal Firmware Engineer will architect and develop firmware for SoC and systems, ensuring customer needs are met and working on complex silicon products.

Architect and develop firmware and microcontroller subsystems for SoC and systems products, ensuring compatibility and implementing features effectively.

As a Senior Physical Design Engineer, you will lead physical implementation from RTL to GDSII for high-speed designs and ensure timing and power closure, involving collaboration across teams to resolve challenges in advanced technology nodes.

The role involves developing and executing verification plans for PCIe and CXL protocols, collaborating with designers, and utilizing coding and protocol expertise for functional verification.

Lead Software QA Engineer responsible for PCIe switch testing, developing test strategies, automation, and mentoring team members, ensuring quality in data-centric systems.

Oversee the design of connectivity ASICs, coordinating with engineering teams and ensuring timing closure and physical design tasks are met.

The Firmware Engineering Manager will oversee BootROM firmware development and simulation modeling, ensuring robust integration of security features and hardware/firmware co-design.

Lead the design and development of firmware for CXL memory expansion products. Collaborate with teams, debug systems, and implement low-level firmware.

The Senior Employment Counsel advises on employment law, manages litigation, oversees policies, provides training, and supports HR compliance in a corporate setting.

Join the DSP SerDes team at Astera Labs to develop high-speed SerDes wireline and optical transceivers. You'll be responsible for coding in System Verilog, collaborating on architecture, and addressing design challenges.

Design and optimize power delivery systems for ASIC products, ensuring robust integrity and developing board-level designs while collaborating with vendors and teams.

Design layout for advanced node CMOS products including floor planning and circuit integration while minimizing parasitic effects and ensuring compliance with EMIR and DRC rules.

Design and implement high-performance digital solutions, focusing on RTL development, IP integration, and overseeing full-chip designs. Collaborate with teams and ensure design verification and timing closure.