The Senior Field Applications Engineer will act as a technical advisor, working with cloud service providers to design solutions using Astera Labs' connectivity products, providing customer support, and driving innovation.

Design and support package substrates for connectivity products, optimizing for performance and reliability in a cross-functional team environment.

Seeking Principal Design Verification Engineer with extensive experience in verification using UVM and C/C++. Responsibilities include automating verification processes, developing tests, and collaborating with RTL designers.

The role involves building diagnostic and manufacturing software for high-speed data center products, from conception to production, requiring strong software and hardware understanding.

Design and implement diagnostics for high-speed digital boards, manage hardware bring-up, validate manufacturing tests, and support software features.

The role involves executing SI planning, design, simulation, and lab validation for connectivity products, focusing on high-speed interconnects and ensuring specification compliance through comprehensive system validation plans.

Lead all engineering activities for ASIC development, ensuring on-time and quality delivery while managing budgets and cross-functional teams.

The Quality Management System Engineer will develop and improve ISO 9001 compliant QMS, lead audits, and enhance quality metrics.

Design and optimize boards for connectivity and memory products, collaborate with customers and internal teams, and ensure successful product manufacturing.

The Senior Firmware Engineer will architect and develop firmware for SoC and systems products, focusing on customer needs and interfacing with hardware teams.

The Principal Data Scientist will develop data solutions, leverage AI/ML methods, and establish analytics frameworks to enhance data-driven decision-making and reporting.

Design and develop firmware for DDR technologies in C, focusing on future products for CXL memory solutions at Astera Labs.

Design and verify advanced CMOS products, focusing on high-speed mixed-signal circuits. Collaborate globally to meet performance goals in a fast-paced environment.

As an Analog Mixed-Signal IC Layout Engineer, you will design advanced CMOS products, manage floor planning, and ensure high-quality layouts for high-speed circuits.

Design and verify advanced node CMOS circuits including PLLs, ADCs, and regulators. Collaborate globally, ensuring performance meets targets.

Design and verify advanced node CMOS products, including complex analog mixed-signal circuits, while collaborating with global teams and driving results.

The Senior Data Scientist will identify key data points, develop data collection strategies, analyze data for insights and work on AI techniques for predictions.

The Senior Digital Design Engineering Manager will lead a team in developing high-speed connectivity solutions, focusing on digital design implementation for ASICs.

The Site HR Manager will oversee HR activities, ensuring compliance with labor laws, managing employee relations, and facilitating recruitment and training. They will promote a positive work environment and manage compensation and benefits programs.

Design and implement high-performance digital solutions, collaborate on IP integration, and ensure timing closure, verification, and debugging.