Jobs at Astera Labs

The Firmware QA Manager will oversee PCIe switch testing, develop test strategies, and mentor team members while ensuring high-quality performance through manual and automated testing.

Lead Firmware QA Engineer responsible for designing and executing tests, collaborating with teams to develop test strategies, and mentoring team members.

The Sales Intern will develop regional sales plans, engage with customers, provide technical support, and forecast regional revenue in collaboration with teams.

Lead and grow a Physical Design team in Hyderabad to deliver end-to-end physical implementation of advanced-node ASICs. Own floorplanning, PnR, CTS, routing, timing/power closure, verification, EDA tool selection, automation, and tapeout schedules while partnering cross-functionally for first-pass silicon success.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

The Senior Physical Design Engineer will manage physical design from RTL to GDSII, ensuring timing and power closure, and collaborate on advanced technology nodes for multi-gigabit transceivers.

Lead sourcing strategy for silicon supply chain categories (Foundry, OSAT, Substrates, Test). Develop should-cost and TCO models, negotiate complex agreements, manage supplier relationships and SRM programs, assess supplier financials and IP, and align sourcing with R&D roadmaps to ensure cost savings, risk mitigation, and business continuity for scale-up AI connectivity products.

The Principal Product Applications Engineer at Astera Labs provides technical guidance to ODMs, supports semiconductor product design, addresses challenges, and improves processes.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Design and implement AI-enabled workflows to accelerate silicon development across frontend and backend design. Build generative AI, RAG, and agentic systems integrated with EDA tools, write production Python/C++ pipelines, process design databases/netlists, and develop evaluation frameworks and benchmarks for design quality.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

The Senior VLSI Design Engineer will design and implement digital blocks for complex semiconductor chips, tackling logic challenges and ensuring robust performance in AI infrastructure solutions.

As a Senior Physical Design Engineer, you will oversee the physical implementation of complex semiconductor designs and guarantee their performance and integrity.

The job involves defining product requirements, engaging with customers, and collaborating with teams to deliver semiconductor products for AI infrastructure.

The Senior Emulation Engineer will execute emulation flows, debug and validate semiconductor chips, and collaborate with cross-functional teams to enhance hardware-software integration.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Responsible for full verification lifecycle of complex ASICs, from planning to debugging coverage measures. Collaborate with design teams and develop test plans.