Jobs at Astera Labs

Architects and implements complex digital blocks and subsystems for high-performance AI connectivity silicon. Owns microarchitecture, RTL, timing closure, DFT, IP integration, verification, sign-off, silicon bring-up, and production delivery. Collaborates across verification, physical design, DFT, firmware, and post-silicon teams while mentoring engineers and improving design methodologies and CAD automation.

Lead verification strategy and execution for complex connectivity IPs and SoCs supporting AI and cloud infrastructure. Architect UVM and SystemVerilog environments, develop coverage-driven and constrained-random methodologies, verify CXL, PCIe, Ethernet, and related protocols, drive debugging, regression automation, coverage closure, and sign-off. Collaborate with architecture, RTL, firmware, emulation, validation, and silicon teams while mentoring engineers and establishing reusable verification frameworks.

Leads design verification for complex connectivity IPs and SoCs using UVM and SystemVerilog. Defines verification strategies, develops reusable environments, drives coverage closure and sign-off, debugs RTL and protocol issues, and leads verification of CXL, PCIe, Ethernet, and related interfaces. Provides technical leadership, mentors engineers, improves automation and methodologies, and collaborates with architecture, RTL, firmware, validation, emulation, FPGA, and silicon teams.

Own the architecture, micro-architecture, RTL implementation, verification, timing closure, DFT, IP integration, and silicon bring-up of complex digital blocks for advanced AI connectivity SoCs. Collaborate with verification, physical design, firmware, and post-silicon teams to deliver production-quality designs using advanced CMOS nodes. Mentor engineers and improve design methodologies and CAD automation.

Architects and implements complex digital blocks and subsystems for high-performance connectivity silicon. Responsibilities include micro-architecture, RTL coding, simulation, synthesis, timing closure, DFT, verification collaboration, IP integration, silicon bring-up, debug, and production delivery. The role leads design ownership from architecture through GDS, collaborates cross-functionally with physical design and firmware teams, improves development processes, and mentors junior engineers.

Own end-to-end RTL-to-GDS physical design for advanced-node, high-performance SoCs, including synthesis, floorplanning, placement, clock-tree synthesis, routing, timing, power, physical verification, and tapeout signoff. Lead methodology development, ECO closure, and cross-functional integration with RTL, DFT, analog, package, and CAD teams. Mentor engineers and guide technical decisions across complex connectivity silicon programs.

Architect and implement complex digital blocks and subsystems for high-performance semiconductor connectivity products. Responsibilities include micro-architecture, RTL coding, verification collaboration, timing closure, DFT implementation, silicon bring-up, debug, and production delivery. The role owns designs from architecture through GDS, collaborates across verification, physical design, DFT, and firmware teams, mentors engineers, and improves silicon development processes and methodologies.

Design and implement synthesizable Verilog/SystemVerilog RTL for high-performance ASIC connectivity products. Responsibilities include translating specifications into digital logic, supporting verification, synthesis, static timing analysis, timing closure, DFT, power optimization, and implementation signoff. The engineer will collaborate with physical design, firmware, systems, and validation teams through tapeout and silicon bring-up, debugging simulation and timing issues and contributing to reliable, reusable designs.

Designs and implements front-end digital circuits for high-performance networking and switch ASICs, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Owns complex designs from architecture through GDS and production while working with PCIe, UALink, Esun, and Ethernet protocols. Requires expertise with Synopsys or Cadence flows, UVM verification, small-geometry CMOS, and customer-focused technical leadership.

Develop and maintain UVM-based verification environments for complex connectivity silicon. Create verification plans, constrained-random tests, assertions, coverage models, VIP integrations, and automated regression infrastructure. Debug simulation, co-simulation, and FPGA emulation failures while collaborating with RTL designers. Verify protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB, and contribute to technical reviews and verification closure.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through verification, silicon bring-up, characterization, and debug in advanced FinFET processes. Establish design methodologies, collaborate across engineering teams, conduct technical reviews, and mentor analog engineers developing connectivity products for AI infrastructure.

Own static timing analysis, signoff, and timing closure for complex ASIC and SoC designs from synthesis through tape-out. Analyze MCMM timing across functional and test modes, debug setup, hold, clock, and variation-related violations, develop SDC constraints, support timing ECOs, and collaborate with RTL, synthesis, physical design, CTS, and signoff teams. Develop Tcl/Python automation, improve timing methodologies, mentor junior engineers, and deliver against tape-out schedules.

Leads physical design for complex SoC and silicon products from architecture through GDSII and production. Owns synthesis, place and route, clock tree synthesis, timing closure, static timing analysis, physical verification, formal equivalence, DFT, ECOs, and backend methodologies for advanced process technologies. Collaborates with IP vendors and cross-functional teams, uses Cadence or Synopsys tools, and develops scripts in Python or Perl.

Design and integrate high-performance connectivity silicon for AI infrastructure, including PCIe and Ethernet controllers, bridges, switches, and SerDes-related IP. Responsibilities span microarchitecture, SystemVerilog or Verilog RTL, synthesis, timing closure, IP integration, DFT, clock-domain crossing, simulation, emulation, and full-chip implementation through GDS handoff. Collaborate with verification, physical design, firmware, and system teams while automating workflows with Python or Perl.

Architect and develop firmware and microcontroller subsystems for SoC and systems products. Build C/C++ firmware and SDKs, boot ROMs, secure boot flows, and hardware-software interfaces. Collaborate with logic designers, conduct pre-silicon simulation and emulation, develop unit tests, and support software build, source-control, code-review, and CI workflows. The role is customer-facing and requires independently prioritizing multiple tasks while supporting complex server, storage, and networking silicon products.

Execute and monitor automated and semi-automated production tests for semiconductor devices. Troubleshoot hardware, software, equipment, and product failures; analyze test data and yields; support new product introduction and test-plan validation; maintain calibration of test systems and fixtures; and document procedures, defects, and compliance results. Collaborate with design and production teams to improve test coverage, process stability, and manufacturing quality.

Leads RTL and microarchitecture development for UALink IP and subsystems, designing high-performance control and data-path logic for scalable, low-latency interconnects. Responsibilities include buffering, arbitration, flow control, ordering, error handling, optimization, SystemVerilog development, debugging, silicon support, cross-functional collaboration, RTL review, and mentoring engineers.

Supports G&A and engineering leaders as an HR advisor, coach, and partner. Responsibilities include employee relations, workplace investigations, employment-law compliance, performance management, talent reviews, organizational design, workforce planning, compensation support, and manager development. The role partners with HR Operations, Legal, Compensation, and Centers of Excellence to scale effective people practices and address talent, retention, and engagement needs.

Leads package signal and power integrity architecture, simulation, optimization, and signoff for advanced semiconductor packages and high-speed connectivity products. Responsibilities include SI/PI modeling, SerDes and PCIe/CXL analysis, PDN design, chip-package-board co-design, advanced packaging integration, simulation-to-measurement correlation, routing guidelines, methodology development, vendor coordination, and mentoring. The role requires cross-functional technical leadership through production ramps while balancing performance, cost, manufacturability, reliability, yield, and schedule.

Architects and maintains ASIC and SoC emulation environments for pre-silicon validation. Integrates RTL, transactors, protocol models, software, and test infrastructure for hardware-software co-simulation. Verifies PCIe, Ethernet, memory, storage, and other interfaces; develops reusable models, tests, checkers, and debug methods; analyzes coverage and performance; and leads cross-functional debugging across design, verification, firmware, and systems teams.