Jobs at Astera Labs

Lead sourcing strategy for silicon supply chain categories (Foundry, OSAT, Substrates, Test). Develop should-cost and TCO models, negotiate complex agreements, manage supplier relationships and SRM programs, assess supplier financials and IP, and align sourcing with R&D roadmaps to ensure cost savings, risk mitigation, and business continuity for scale-up AI connectivity products.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

The Senior VLSI Design Engineer will design and implement digital blocks for complex semiconductor chips, tackling logic challenges and ensuring robust performance in AI infrastructure solutions.

As a Senior Physical Design Engineer, you will oversee the physical implementation of complex semiconductor designs and guarantee their performance and integrity.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.

The job involves defining product requirements, engaging with customers, and collaborating with teams to deliver semiconductor products for AI infrastructure.

The Senior Emulation Engineer will execute emulation flows, debug and validate semiconductor chips, and collaborate with cross-functional teams to enhance hardware-software integration.

The Principal Product Applications Engineer at Astera Labs provides technical guidance to ODMs, supports semiconductor product design, addresses challenges, and improves processes.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

Build and operate ML infrastructure for LLMs and agent systems: model gateways, routing, serving, telemetry, observability, evaluation, cost-aware routing, dashboards, and APIs/SDKs to enable reliable production AI at scale.

The Principal Product Applications Engineer will engage with customers, support PCIe product adoption, troubleshoot system issues, and create technical documentation while collaborating with cross-functional teams.

The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.

The Lead ATE Test Engineer develops and oversees SoC test strategies, collaborates with teams, defines ATE programs, and ensures high-quality product transition to manufacturing.