Jobs at Astera Labs

Lead functional verification for advanced ASICs and SoCs, including test planning, SystemVerilog/UVM development, constrained-random testing, debugging, coverage analysis, and coverage closure. Collaborate with RTL designers, software teams, and system validation teams on emulation and hardware-software co-verification. Drive verification methodologies for server and networking applications, including switching architectures, packet processing, PCIe, Ethernet, and NoC designs.

Leads the Toronto physical design engineering team and owns ASIC implementation from RTL through GDSII and tapeout. Responsibilities include floorplanning, place-and-route, CTS, timing closure, extraction, EM-IR, DRC/LVS, equivalence checking, IP integration, methodology development, cross-functional convergence, hiring, mentoring, and coordination with global physical design teams. The role focuses on high-speed connectivity ASICs, including retimers and signal-conditioning products, using advanced-node semiconductor technologies.

Leads strategic sourcing across semiconductor supply-chain categories including foundries, OSATs, substrates, and test providers. Develops category strategies, analyzes supplier capabilities and costs, builds should-cost and TCO models, negotiates complex agreements, manages supplier relationships, mitigates supply risk, and aligns sourcing decisions with technology roadmaps. Partners with engineering, R&D, and global stakeholders to support product development, capacity, cost savings, supplier performance, and business continuity.

Owns full-chip and block-level physical design from architecture through GDSII and production. Responsibilities include synthesis, place and route, clock tree synthesis, timing closure, formal equivalence verification, physical verification, DFT, ECO implementation, and collaboration with RTL and hard-macro IP vendors. The role supports complex SoC and silicon products for server, storage, and networking applications using advanced process technologies.

Design, develop, and deploy LLM-powered agentic applications for RTL, physical and analog design, linting, static analysis, and formal verification. Build engineering assistants, dialogue systems, retrieval infrastructure, databases, and dashboards integrated with CAD/EDA workflows. Collaborate with hardware design, design verification, formal verification, and CAD teams to identify challenges and deliver AI-assisted tools. Apply software engineering and AI/ML expertise to accelerate debugging, coverage closure, lint analysis, RTL optimization, and formal proof convergence.

Leads end-to-end engineering programs for analog/mixed-signal semiconductor IP, from specification through tape-out and silicon validation. Coordinates circuit design, layout, verification, systems, product, operations, foundries, and vendors. Owns schedules, milestones, budgets, metrics, risks, stakeholder communication, and program reviews while driving process improvements and resolving cross-functional blockers.

Lead the end-to-end development and technical direction of internal automation platforms. Build full-stack features, backend services, frontend interfaces, databases, access controls, approval workflows, dashboards, and integrations with SaaS, cloud, and identity systems. Automate IT, HR, and Finance workflows involving onboarding, offboarding, asset tracking, entitlements, audit logging, and access reviews. Personally write code, evolve schemas, maintain testing, establish engineering standards, and use AI-assisted development tools.

Architects and develops firmware and microcontroller subsystems for SoC and systems products. Responsibilities include C/C++ firmware and SDK development, Python scripting, HW-SW interface implementation and testing, unit testing, build automation, source control, CI workflows, and collaboration with hardware designers and customers. Preferred work includes RTOS, boot ROM, pre-silicon simulation and emulation, and secure boot technologies.

Own RTL synthesis, SDC constraint development, MMMC setup, and STA timing closure for high-speed SerDes digital and mixed-signal ASIC designs. Optimize area, power, and timing; manage advanced-node signoff, timing budgets, ECOs, hierarchical analysis, and clock/power-domain strategies. Collaborate with analog, RTL, physical design, verification, and architecture teams to achieve block- and full-chip timing convergence.

Leads and develops a US-based technical program management team responsible for advanced ASIC programs from architecture through production release. Oversees milestone planning, dependencies, execution reviews, risk mitigation, budgeting, resource allocation, and readiness for tapeout, power-on, validation, qualification, and manufacturing. Partners with engineering, executives, customers, and external partners while driving consistent reporting, accountability, and cross-functional issue resolution.

Develop microarchitecture and front-end digital designs for high-performance networking and switch ASICs. Own RTL, synthesis, IP integration, verification, timing closure, DFT, and block or full-chip implementation through GDS and production. Apply PCIe, UALink, Esun, and Ethernet protocol expertise while using Synopsys or Cadence flows. Support silicon bring-up and debugging, collaborate with customers, and drive multiple complex designs with minimal supervision.

Perform block-level and top-level physical design implementation for high-speed transceiver IPs at advanced technology nodes. Responsibilities include floorplanning, placement, CTS, routing, physical verification, timing and power optimization, EM/IR analysis, congestion mitigation, ECOs, IP integration, and tapeout signoff. The role also requires scripting automation and collaboration with RTL, STA, and cross-functional engineering teams.

Design and verify analog and mixed-signal IC layout blocks for high-performance ASICs using advanced CMOS processes. The role requires hardware engineering expertise in VLSI or computer architecture, RTL design and verification skills, scripting, and C/C++ experience. Preferred qualifications include experience with PCIe, DDR, HBM, SerDes, real-world semiconductor design, and Synopsys EDA tools.

Design and verify advanced-node CMOS analog and mixed-signal ICs, including PLLs, ADCs, regulators, amplifiers, transmitters, receivers, and clocking circuits. The role requires transistor-level design, tapeout, lab bring-up, debugging, noise and jitter analysis, and collaboration across global teams. Engineers will use Spectre and MATLAB, contribute to connectivity and optical applications, and apply expertise in RFIC design, PCB development, ESD protection, packaging, and high-speed data transmission.

Design and verify analog and mixed-signal IC layout blocks for advanced CMOS ASICs supporting high-performance computing and networking. The role involves RTL and hardware verification using Verilog, SystemVerilog, UVM, assertions, and functional coverage, along with scripting in Python or Perl and development in C/C++. Familiarity with PCIe, DDR, HBM, SerDes, and Synopsys EDA tools is preferred.

Lead block-level and top-level physical implementation for high-speed transceiver IPs at advanced technology nodes. Responsibilities include floorplanning, placement, CTS, routing, timing and power convergence, EM/IR analysis, congestion mitigation, physical verification, IP integration, ECOs, and tapeout signoff. The role requires collaboration with RTL and STA teams, automation scripting, and hands-on use of industry-standard implementation and signoff tools.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, and high-speed I/O products. Lead designs from specification through schematic, layout supervision, verification, silicon bring-up, characterization, and debug. Establish design methodologies, collaborate across engineering teams, and mentor analog engineers. The role requires advanced CMOS/FinFET design expertise, physical-layer and signal-integrity knowledge, and proficiency with industry-standard simulation tools.

Own PCBA planning from early engineering builds through production ramp. Build and maintain plans covering bills of material, material availability, purchase orders, supplier commitments, inventory, shortages, and production milestones. Coordinate hardware engineering, procurement, operations, contract manufacturers, suppliers, and testing teams. Identify supply, capacity, and schedule risks, drive mitigation plans, support order fulfillment, and prepare readiness reports and operating metrics.

Owns semiconductor physical design from architecture through GDSII and production. Responsibilities include synthesis, place and route, clock tree synthesis, timing closure, formal equivalence verification, physical verification, DFT, ECOs, and backend tool flows for advanced-node SoCs. The role collaborates with IP vendors, supports complex server, storage, and networking silicon products, and uses Cadence or Synopsys tools plus Python or Perl scripting.

Owns PCBA new product introduction planning from engineering builds through production ramp. Develops build plans, tracks BOM readiness, materials, inventory, purchase orders, supplier commitments, and manufacturing milestones. Coordinates engineering, procurement, suppliers, contract manufacturers, and quality teams to resolve shortages, capacity constraints, schedule risks, and execution issues. Supports order fulfillment, readiness reviews, launch communications, and data-driven improvements to schedule predictability and inventory efficiency.