Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Are you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera’s development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers’ bottlenecks in hyperscale data centers.
This role is fully in person, in San Jose. Some travel may be required.
Basic qualifications
- BS in Electrical or computer engineering, MS or PhD preferred.
- ≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers
- Deep experience with PCIe 5/6, and CXL including protocol level depth
- Expertise in OS software integration including memory allocation/management
- Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)
- Deep expertise and understanding of memory components (DRAM, etc)
- Strong understanding of datacenter system architecture and design challenges
- Strong understanding of “full stack” solutions from silicon to application integration
- Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases
- Ability to dig deeply into technical challenges and use cases
- Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners.
- Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment.
- Willingness to travel occasionally for customer meetings and industry events.
Preferred experience
- Expertise in JEDEC-defined memory interface specifications
- Expertise in memory ECC and error handling
- Experience in product integration with BIOS, kernel, OS, tooling, and BMCs
- Experience with board and system design
- Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.
- Hands-on silicon development experience
Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- BS in Electrical or Computer Engineering, MS or PhD preferred
- 10+ years experience developing memory-related solutions for data centers
- Deep experience with PCIe 5/6 and CXL
- Expertise in OS software integration including memory management
- Experience with silicon architecture and SOCs with memory controllers
- Strong understanding of datacenter system architecture and design
- Experience in customer-facing role and ability to articulate technical concepts
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
