Senior Principal ASIC Design Engineer

Location: Germany (on-site)

Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.

You will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon.

• Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.
• Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.
• Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.
• Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.
• Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.
• Serve as a technical authority across digital, networking, and system domains.

• Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.
• Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.
• Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration.
• Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service.
• Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics.
• Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.
• Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.
• Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.
• Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.
• Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.
• Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.
• Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.
• Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.
• Demonstrated technical leadership across multiple teams and product programs.

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.
• Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.
• Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.
• Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.
• Excellent communication, collaboration, and mentorship skills.