Teams at Astera Labs

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.

The Senior Principal Engineering Program Manager will lead ASIC product development, ensuring timely execution, risk management, and cross-functional alignment across various teams to deliver revenue-critical silicon solutions.

The Senior Principal Technologist will drive the architecture and development of data center memory solutions, engage with customers, and influence product features using expertise in system and memory architecture and technologies.