Teams at Astera Labs

Leads DFT architecture and execution for high-speed PCIe and Ethernet signal-conditioning products. Defines test, coverage, observability, diagnostics, scan, ATPG, MBIST, LBIST, JTAG, and SerDes BIST strategies across advanced multi-die designs. Partners with design, verification, packaging, manufacturing, and test teams through tape-out, silicon bring-up, yield analysis, and production ramp. Mentors engineers, coordinates cross-functional execution, and works with OSATs and ATE vendors to improve quality, manufacturability, and production readiness.

Leads full-chip static timing analysis signoff and timing closure for complex AI connectivity SoCs across advanced process nodes. Develops STA methodologies, SDC constraints, and automated PrimeTime-based flows; resolves setup, hold, CDC, crosstalk, noise, and IR-aware timing issues. Partners with physical design, RTL, DFT, CAD, package, and low-power teams from floorplanning through tapeout. Mentors engineers, reviews signoff collateral, investigates silicon timing issues, and guides EDA tooling and methodology strategy.

Architects and implements complex digital blocks and subsystems for high-performance AI connectivity silicon. Owns microarchitecture, RTL, timing closure, DFT, IP integration, verification, sign-off, silicon bring-up, and production delivery. Collaborates across verification, physical design, DFT, firmware, and post-silicon teams while mentoring engineers and improving design methodologies and CAD automation.