Top Senior Hardware Engineer Jobs in Greensboro, NC

Maintains and troubleshoots server, storage, networking, cabling, and power hardware across a large-scale production data center fleet. Writes Python automation scripts, reviews logs and alerts, performs diagnostics, supports deployments, builds hardware health dashboards, coordinates with DevOps, supply chain, and vendors, and assists with hardware evaluation and reliability improvements. Requires on-call availability and travel to data center sites.

Designs and develops hardware boards and systems for Cisco routing products, spanning architecture, schematic design, development, bring-up, validation, testing, qualification, and production readiness. Collaborates with software, diagnostics, manufacturing, marketing, and test teams. Requires extensive experience with x86 or ARM processors, DDR memory, high-speed interfaces, signal integrity, power distribution, Ethernet, FPGA technologies, and schematic capture tools.

Tests, validates, and troubleshoots next-generation cloud server hardware for performance, power, reliability, and quality. Develops test scripts, documents results, identifies defects, recommends improvements, and resolves hardware issues across engineering and manufacturing environments. Requires hands-on embedded systems debugging, Linux and scripting experience, and knowledge of server architecture, firmware, operating systems, networking, storage, and hardware acceleration technologies.

Develop and operate Akamai’s Linux-based cloud infrastructure, including bare-metal and virtual machine platforms, kernels, operating systems, and KVM/QEMU virtualization. Build software, automation, observability, and infrastructure enhancements at scale; troubleshoot complex distributed-system issues; collaborate across engineering and operations; mentor team members; and participate in on-call service restoration.

Designs and develops FPGA SmartNIC networking acceleration for Microsoft Azure. Responsibilities include hardware architecture evaluation, RTL coding in Verilog/SystemVerilog, simulation, hardware testing, debugging, verification, scripting, software development, Agile collaboration, and production DevOps support. The role partners across hardware and software teams to deliver cloud networking infrastructure, including SDN capabilities, packet manipulation, and performance improvements.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

Owns the hardware lifecycle for GPU and infrastructure assets, including fleet health monitoring, vendor RMA workflows, firmware and BIOS upgrades, burn-in testing, failure investigation, inventory accuracy, capacity planning, spare-parts strategy, runbook creation, and new platform qualification. The role serves as the technical owner of physical compute platforms and supports high-density GPU infrastructure across sites.

Develop and own compute and GPU server platforms from architecture through global deployment. Responsibilities include schematic and layout reviews, design for manufacturability, new product introduction, board and system bring-up, validation, debugging, firmware and BIOS feature management, technology qualification, and vendor coordination. The role requires hands-on server architecture, board-level design, Linux and scripting expertise, platform validation, and five-day-per-week presence in the Cambridge office.

Pipeline hiring for hardware engineers at all experience levels. Work includes circuit board design, schematic capture, component selection and prototype bring-up, hardware debug/testing and failure analysis, integration with firmware/software teams, and design for manufacturability with production handoff.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Lead SI/PI technical work for next-generation ASIC packaging: define design rules, run pre/post-layout SI/PI simulations, analyze substrate SI/PI, collaborate with layout and system teams, mentor engineers, and drive packaging design and validation for high-performance ASICs.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.