Principal Physical Design Engineer

Principal Physical Design Engineer

  

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Job Description:

   

Job Summary

We are seeking a highly skilled Physical Design Flow and Place‑and‑Route (P&R) Development Engineer to drive methodology, automation, and implementation solutions for advanced ASIC designs. The ideal candidate will have deep experience with Cadence Innovus, Synopsys Fusion Compiler, and modern RTL‑to‑GDS flows. This role focuses on developing scalable P&R methodologies, improving flow robustness, and partnering with design teams to deliver high‑quality, high‑performance silicon.

Key Responsibilities

P&R Flow Development & Methodology (Main Responsibility)

• Develop, maintain, and enhance RTL‑to‑GDS flows using Innovus and Fusion Compiler.
• Create robust, repeatable methodologies for floor planning, placement, CTS, routing, and optimization.
• Automate flow steps using Tcl, Python, and Make file‑based infrastructures.
• Investigate and deploy new tool features, optimization techniques, and technology‑node‑specific capabilities.

Physical Design Support

• Partner with RTL designers, analog/mixed‑signal teams, and PD implementers to support full‑chip and block‑level P&R execution.
• Provide hands‑on support for floorplan definition, clock topology, power grid planning, placement optimization, timing closure, IR/EM mitigation, and DRC fixing.
• Debug tool issues, convergence challenges, and signoff discrepancies across STA, LVS, DRC, and extraction.

Implementation Quality & Signoff

• Ensure P&R flows achieve best‑in‑class results on timing, area, power, noise, and DRC.
• Drive correlation improvements between FC/Innovus and signoff tools (PrimeTime, StarRC, Voltus, RedHawk, Calibre).
• Define and enforce physical signoff criteria and quality metrics.

Cross‑Team Collaboration

• Interface with EDA, library/PDK, signoff, and architecture teams to support technology bring‑up and design scalability.
• Help evaluate new EDA tools, PDK features, and design methodologies for next‑generation technologies and products.

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 7–10+ years of experience in ASIC physical design flows or physical design methodology.
• Strong expertise in:
  • Cadence Innovus place and route, and/or
  • Synopsys Fusion Compiler
  • Physical design fundamentals (floorplan, placement, CTS, routing, ECO flows)
  • Timing concepts (setup/hold closure, OCV/AOCV/POCV, derates)
  • Power/thermal integrity (IR drop, EM reliability)
  • DRC/LVS and physical signoff flows
• Strong scripting skills in Tcl, Python, and Linux shell.
• Ability to troubleshoot complex tool, flow, or methodology issues across PD and signoff.

Preferred Qualifications

• Experience with advanced process nodes (7 nm, 5 nm, or below).
• Familiarity with UPF/low‑power flows, multi‑clock-domain designs, and hierarchical P&R.
• Experience with version control systems (Git/Perforce) and CI automation.
• Knowledge of extraction, STA signoff, and parasitic modeling (StarRC, PrimeTime).
• Strong problem‑solving skills and ability to drive issues to closure.

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Job:

Engineering

Job Level:

TCP_05

    

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

   

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

   

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