Jobs at Ixana

Design and lead development of miniaturized PCBs for wearable devices using custom Wi-R ICs and COTS components. Create schematics and layouts, perform board-level testing and debugging, collaborate on packaging, and support prototype validation and test automation.

Design, analyze, and tape-out low-power mixed-signal and RF circuits for wearable communication chips. Integrate analog IP into SoCs, verify and validate designs, collaborate with firmware/board/testing teams, and perform lab validation from schematic through layout and tape-out.

Work on designing, simulating, and prototyping ultra-low-power wearable and biomedical hardware. Support schematic capture, multilayer PCB layout, component selection, system integration, bring-up, validation, and testing for devices like smartglasses, rings, and watches while collaborating across design, product, and supply chain teams.

Work directly with founders to translate strategy into action, track initiatives, coordinate cross-functional execution, prepare executive briefs, run special projects (fundraising, hiring, partnerships), and manage on-site operations, logistics, and internal operating rhythms.

Work on embedded hardware and FPGA-based wearable systems: assist with schematic capture, multilayer PCB layout, component selection, prototyping, board bring-up, validation, testing, and debugging. Support FPGA implementations for signal processing and interface logic while collaborating with product, industrial design, and supply chain teams.

Lead development of bare-metal C/C++ firmware for ultra-low-power wearable devices using Ixana's Wi-R technology. Build, test, and debug MCU firmware, integrate I2C/SPI/BLE protocols, optimize for low power, and collaborate with hardware and systems engineers to bring up reference devices and define the Wi-R embedded standard.

Lead architecture and execution of next-generation wearable Wi-R SoCs. Build and manage an IC design team, own RTL-to-GDS tape-outs, drive analog/RF front-end and mixed-signal integration, define verification/IP reuse methodology, and coordinate silicon validation, packaging, and product co-optimization with cross-functional teams.

Lead and grow a world-class IC design organization across analog, mixed-signal, RF, and digital domains. Own end-to-end chip lifecycle from concept through GDSII, tapeout, bring-up and production. Set architecture and technical standards, guide EDA tool and vendor engagements, integrate IP, coordinate with hardware/firmware/product teams, hire and mentor engineers, and represent engineering in executive strategy and partnerships.

Lead design, simulation, prototyping, and launch of wearable embedded hardware. Own schematics, multilayer PCB layout, system integration, component selection, validation, bring-up, and cross-functional coordination for smart devices.

Manage on-site office operations, vendor coordination, procurement, and facilities upkeep. Provide first-line IT support, maintain Wi‑Fi, access control, asset inventory, onboarding/offboarding accounts, and coordinate logistics for shipping, events, and team travel.

Design, develop, and deliver FPGA-based emulation platforms and FPGA models for digital/analog IP to enable pre-silicon verification, prototype bring-up, and software integration. Collaborate cross-functionally, create pre-silicon validation test plans, and support emulation lab bring-up and debugging.

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

Lead end-to-end analog/mixed-signal IC design from specification to tapeout, drive circuit innovation to meet power/performance/area goals, collaborate with digital/layout/product teams, recruit and mentor engineers, own technical decision-making, and oversee board-level bring-up, test automation, and PCB design for production at scale.

Plan and execute end-to-end RTL verification for SoCs and IPs using SystemVerilog and UVM. Build testbenches with functional coverage and assertions, perform gate-level and power-aware verification, debug waveforms, script automation, and collaborate with design, architecture, and system teams to deliver silicon.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Lead analog and mixed-signal IP design, verification, and integration for Wi-R SoCs. Drive RF IC architecture through post-silicon bring-up, collaborate with firmware/digital/board teams, mentor junior engineers, and publish technical results. Own end-to-end chip development and long-term technical strategy for ultra-low-power wireless silicon.

Lead bare-metal bring-up of Wi-R SoCs and Cortex-M/RISC-V platforms, develop and optimize ultra-low-power firmware stacks (I2C, SPI, BLE, DMA, sensor drivers), deliver a production-ready firmware SDK, debug at register level using oscilloscopes and JTAG, mentor junior engineers, and drive toolchain and quality standards across teams.

Develop wearable and implantable medical devices around Wi‑R SoCs: drive schematic and 4‑layer medical PCB design, firmware bring‑up, benchtop and in‑vivo testing, and design for FDA Class II/III including biocompatibility and ISO 13485 documentation. Collaborate across IC, RF, mechanical, and clinical teams; publish and patent work.