Teams at Ixana

Plan and execute end-to-end RTL verification for SoCs and IPs using SystemVerilog and UVM. Build testbenches with functional coverage and assertions, perform gate-level and power-aware verification, debug waveforms, script automation, and collaborate with design, architecture, and system teams to deliver silicon.

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

Lead bare-metal bring-up of Wi-R SoCs and Cortex-M/RISC-V platforms, develop and optimize ultra-low-power firmware stacks (I2C, SPI, BLE, DMA, sensor drivers), deliver a production-ready firmware SDK, debug at register level using oscilloscopes and JTAG, mentor junior engineers, and drive toolchain and quality standards across teams.