This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
We are seeking a talented and driven Senior Design Verification Engineer with specialized knowledge and experience in emulation-based verification to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.
Responsibilities
Develop and execute verification plans for IP-level and system-level designs.
Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.
Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation.
Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.
Drive coverage closure and generate verification sign-off reports.
Support software and firmware teams with early bring-up activities on emulation platforms.
Continuously improve verification processes, flows, and infrastructure.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
5 – 8 years of professional experience in design verification of digital/mixed-signal designs.
Strong proficiency in SystemVerilog and UVM methodology.
Hands-on experience with emulation-based verification platforms (e.g., Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).
Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.
Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.
Proficiency in debugging complex hardware designs using simulation and emulation tools.
Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.
Strong analytical and problem-solving skills with excellent attention to detail.
Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Experience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.
Knowledge of communication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.
Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).
Familiarity with FPGA prototyping platforms and flows.
Experience with power-aware verification (UPF/CPF).
Prior exposure to SoC-level verification or full-chip integration verification.
Knowledge of processor architectures (ARM, RISC-V, x86) and software-driven verification techniques.
Experience with continuous integration (CI) and regression management frameworks.
Familiarity with AI/ML application and architectures and experience, such as, creating Gen AI skills, marketplace, agentic applications, etc.
Published work or patents in the area of design verification is a plus.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
Job:
EngineeringJob Level:
TCP_04"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 153,500 - 310,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
- 5 - 8 years professional experience in design verification of digital/mixed-signal designs.
- Strong proficiency in SystemVerilog and UVM methodology.
- Hands-on experience with emulation-based verification platforms (Cadence Palladium, Synopsys ZeBu, Mentor Veloce).
- Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.
- Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.
- Proficiency in debugging complex hardware designs using simulation and emulation tools.
- Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.
- Strong analytical and problem-solving skills with excellent attention to detail.
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.
- Knowledge of communication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.
- Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).
- Familiarity with FPGA prototyping platforms and flows.
- Experience with power-aware verification (UPF/CPF).
- Prior exposure to SoC-level verification or full-chip integration verification.
- Knowledge of processor architectures (ARM, RISC-V, x86) and software-driven verification techniques.
- Experience with continuous integration (CI) and regression management frameworks.
- Familiarity with AI/ML application and architectures and related verification scenarios.
- Published work or patents in design verification.
Hewlett Packard Enterprise Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Hewlett Packard Enterprise and has not been reviewed or approved by Hewlett Packard Enterprise.
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Parental & Family Support — Parental leave provides six months of fully paid time for all parents and includes options to return part-time for up to 36 months. Additional supports like backup childcare, fertility and adoption assistance reinforce a family-friendly package.
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Wellbeing & Lifestyle Benefits — Wellness Fridays offer paid early-finish time each month alongside resources such as on-site gyms, mental health tools, and paid volunteer time. These programs emphasize balance and personal well-being.
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Retirement Support — Retirement programs include a 401(k) with a 100% match on the first 4% of base salary and an Employee Stock Purchase Program. Retirement Transition Support enables part-time work for employees nearing retirement.
Hewlett Packard Enterprise Insights
What We Do
In 1939, Bill Hewlett and Dave Packard, college friends turned business partners, started the original Silicon Valley startup in the space of a rented Palo Alto garage. Starting with audio oscillators, the friends built the foundation for a company that would grow to become a global leader in enterprise technology. More than 75 years later, our success is exemplified through our employees’ drive to advance ideas that bring meaningful innovations to life for our customers and partners around the globe. We are guided by our mission to help customers use technology to turn ideas into value, and empower them to transform industries, markets and lives. We simplify Hybrid IT, power the Intelligent Edge and provide the expertise to make it all happen.
