Jobs at Microchip Technology Inc.

Support and optimize photolithography processes for PLP and WLCSP, monitor critical parameters (resist thickness, CD, overlay, defects), drive defect reduction and cycle-time improvements, perform data analysis and RCA, coordinate tool maintenance and calibration, support NPI and process qualification, and maintain work instructions and process documentation.

Lead architecture, RTL design, and verification of multi-gigabit Ethernet PHY digital blocks using industry-standard ASIC flows. Perform RTL coding, functional verification, pre-silicon FPGA emulation, synthesis/STA, and coordinate silicon bring-up while mentoring junior engineers and collaborating with cross-functional global teams.

Support end-to-end photolithography for PLP and WLCSP: coat/expose/develop, metrology, defect reduction, data analysis, RCA, process optimization, NPI support, and documentation in a cleanroom manufacturing environment.

Provide technical support and training for USB products, debug customer hardware/software implementations, develop evaluation hardware and reference designs, create documentation and application collateral, and collaborate with product marketing and partners to guide product development.

Drive design wins and revenue at assigned semiconductor clients using consultative selling and Microchip's Client Engagement Process. Build and coach client stakeholder consensus, collaborate with global teams and applications engineers, provide product feedback and ROI, and develop sales strategies across divisions and regions.

Design and execute block-level verification for RTL using SystemVerilog and UVM. Develop test plans and testbenches, create and run regression tests, analyze code and functional coverage, integrate with RTL, and collaborate with design teams to debug and resolve issues.

Lead chip-level design and verification for Touch Controller IPs, from specification and architecture through RTL implementation and verification. Contribute to design reviews, documentation, development methodology, project coordination, and cross-functional collaboration.

Support wafer foundry sourcing, supplier negotiations, and cost management. Maintain contracts and negotiation records, analyze wafer/mask/NRE costs, generate pricing reports and scorecards, support RFIs/RFQs, and assess supply resiliency. Prepare negotiation packages and dashboards to inform leadership decisions and track savings from sourcing initiatives.

Lead design and implementation of physical-layer algorithms and PHY modem features for low-power wireless SoCs. Perform system-level trade studies, develop hardware-aware and fixed-point models, support silicon bring-up and lab validation, and coordinate cross-functional teams to ensure production readiness and performance optimization.

Provide technical support to mass-market customers for microcontrollers/microprocessors and embedded firmware/software. Troubleshoot hardware and firmware issues via tickets, phone, and chat; analyze root causes; create example code, KB articles, application notes, and training; collaborate with product and field teams; use lab instruments; apply AI/ML familiarity to support workflows and improve customer outcomes.

Design and develop advanced connectivity devices (Ethernet switches/bridges, USB hubs/PD, PCIe bridges, SerDes). Perform digital design using Verilog/SystemVerilog, participate in ASIC design/verification flows, simulate and debug designs, and collaborate closely within a cross-functional engineering team to bring products to market.

Drive revenue growth with strategic storage, data center, communications, and hyperscale OEM accounts. Own account plans, expand executive and engineering relationships, identify design-win opportunities, coordinate cross-functional teams, manage customer engagements, and meet sales targets with regular customer visits.

Lead and develop a global applications engineering organization for Analog Power products. Set strategy and roadmaps with marketing and engineering, manage resource allocation, enable FAEs, drive cross-functional new product execution, engage with clients and IC architects, and monitor market and competitive trends to deliver system-level power solutions.

Lead physical implementation of mixed-signal, low-power microcontroller SOCs from netlist to GDSII. Perform floorplanning, placement, CTS, timing closure, power integrity/IR drop and EM signoff, physical verification (DRC/LVS), metal-only ECOs, and collaborate with IP, CAD, synthesis, and DFT teams to ensure timely tapeout and first-pass silicon success.

Lead and scale a global SoC verification team (20+ engineers) to deliver first-pass silicon success for 32-bit MCU projects. Own verification strategy, testbench architecture, UVM and formal flows, power-aware verification, coverage-driven metrics, regression management, and cross-functional integration with architecture, RTL, DSP, and physical design teams. Drive automation and scripting to improve verification efficiency.

Lead IP-level verification for dsPIC products by architecting and maintaining UVM and formal verification environments, writing SystemVerilog assertions and coverage, debugging RTL/testbench issues, integrating IP tests into SoC environments, mentoring verification engineers, and improving methodologies using AI/ML automation to meet schedule and quality targets.

Lead full-chip and large block physical design from RTL to GDSII across advanced nodes (40nm to 3nm+). Responsibilities include floorplanning, place-and-route, CTS, timing closure, physical verification, IR/EM checks, IP integration, mentoring junior engineers, and using metric-driven flows to achieve first-pass silicon.

Lead a small team to design and implement firmware/embedded software verification for SoC and Ethernet PHY devices. Define test plans, build test frameworks and CI/CD regression, run pre- and post-silicon testing on FPGA/boards, debug firmware/hardware interactions, coordinate globally, and mentor engineers.

Validate FPGA features and interfaces using RTL and embedded software tests, bring up silicon in lab, debug failures, perform root-cause analysis, document results, and develop automation and regression flows.

Support R&D team in developing microwave acoustic (SAW) RF devices: contribute to CAD tool development, run process and reliability tests, evaluate and document results, and assist process development projects.