Jobs at Lumilens

Develops and executes UVM-based functional verification for chiplet blocks and subsystems. Responsibilities include building testbenches, writing constrained-random tests, achieving coverage closure, integrating VIP, debugging regressions, verifying firmware and mixed-signal models, and supporting emulation, FPGA prototyping, gate-level, and low-power verification. The role collaborates with design, architecture, modeling, and DFT teams through signoff.

Develop C#/.NET desktop manufacturing software for optical transceiver testing. Build WPF/MVVM interfaces, concurrent test execution, hardware drivers, instrument resource management, RPC services, and embedded Python testing capabilities. Design reliable, testable systems using clean architecture, MongoDB, GitHub Actions, and automated deployment to Windows machines. Diagnose distributed failures through logs and telemetry while supporting software operating at manufacturing scale.

Leads end-to-end design verification for a photonics chiplet, defining verification strategy, UVM architecture, coverage, signoff, regressions, emulation, FPGA prototyping, UCIe compliance, mixed-signal co-simulation, low-power and gate-level verification. Owns performance validation, firmware and boot-flow verification, and grows a cross-functional DV team across FEC, UCIe, MCU, datapath, and full-chip domains.

Own end-to-end design verification for a photonics chiplet, defining verification strategy, coverage, UVM architecture, regressions, emulation, FPGA prototyping, mixed-signal co-simulation, UCIe compliance, performance validation, gate-level and low-power signoff. Lead and grow a distributed DV team while driving verification across FEC, interconnect, MCU, datapath, and full-chip systems through tapeout.

Designs high-speed analog and MMIC circuits for photonic interconnects from architecture through tapeout and silicon validation. Responsibilities include schematic design, EM modeling, parasitic extraction, simulation, physical verification, reliability signoff, automation scripting, layout collaboration, and lab characterization. Requires advanced analog IC design expertise, high-frequency analysis, EDA proficiency, and experience with advanced process technologies.

Manage reception, office administration, facilities, supplies, vendors, purchasing, expenses, confidential records, events, travel, and executive support. Ensure smooth daily office operations, maintain shared spaces, coordinate maintenance and service providers, handle calls and visitors, and support meetings and team activities. The role requires strong organization, discretion, communication in English and Chinese, multitasking, and proactive problem-solving in a fast-paced startup environment.

Manages the manufacturing site’s front desk and daily administration. Responsibilities include visitor and contractor access, mail and deliveries, office and facility coordination, inventory, vendor services, HR onboarding logistics, purchasing, expenses, customer and supplier visits, and travel arrangements. The role is fully onsite and requires discretion, strong organization, communication skills, and experience supporting office operations in a manufacturing or high-tech environment.

Lead development and optimization of wafer backside grinding, laser stealth dicing, and die sorting for silicon photonics. Troubleshoot process issues, improve yield and throughput, ensure compatibility with bumping/flip-chip, and produce SOPs, WIs, failure reports, and support NPI and process verification.

Design and implement complex analog, mixed-signal, RF, and connectivity IP layouts from floorplanning through tapeout. Responsibilities include physical verification and signoff using DRC, LVS, ERC, antenna, DFM, and EMIR; optimizing layouts based on extraction results; collaborating with circuit, verification, CAD, and technology teams; and improving productivity through automation, scripting, and AI-assisted workflows.

Design, manage, secure, and optimize Lumilens’s global multi-site LAN, WAN, SD-WAN, VPN, cloud, wireless, and enterprise network infrastructure across India, Thailand, Singapore, and the US. Responsibilities include firewall and network device administration, SASE and Zero Trust deployments, Azure and Microsoft 365 integration, identity-aware access, monitoring, automation, vendor evaluation, documentation, and collaboration with distributed teams.

Investigates optical, electrical, and mechanical failures in optical transceivers from production testing and field deployments. Uses schematics, test equipment, fault isolation, device characterization, and data analysis to identify root causes and recommend corrective actions. Documents findings, assesses field risks, collaborates with R&D, supplier quality, and production teams, develops test infrastructure and automation scripts, and communicates reliability insights to internal teams and customers.

Own strategic sourcing, supplier strategy, negotiations, cost optimization, supply continuity, and supplier performance for photonics products. Build and manage global supplier networks across silicon photonics, advanced packaging, optical components, contract manufacturing, and manufacturing partners. Partner with engineering, operations, manufacturing, and finance to support NPI, supplier qualification, capacity planning, risk mitigation, and transitions to high-volume manufacturing.

Lead global sourcing strategy and end-to-end supply chain management for optical and photonic components. Responsibilities include supplier identification and qualification, capacity and allocation planning, commercial negotiations, cost reduction, supply risk mitigation, dual-sourcing, supplier performance tracking, and cross-functional collaboration with engineering, quality, operations, program management, and contract manufacturing partners.

Develop and optimize optical alignment and assembly processes for photonic products from prototype through NPI and volume manufacturing. Responsibilities include active and passive alignment, epoxy dispensing and curing, equipment qualification, DOE, process characterization, statistical capability analysis, root-cause investigation, yield improvement, documentation, DFM/DFA support, and manufacturing transfer. The engineer will collaborate with R&D, manufacturing, suppliers, quality teams, and contract manufacturers to establish robust processes and production controls.

Manage external semiconductor foundry partnerships and coordinate technical, business, and production deliverables. Lead product transitions from NPI to high-volume manufacturing, improve on-time delivery and cycle time, and resolve yield, RMA, and process-excursion issues. Oversee root-cause analysis, corrective actions, quality metrics, process change notifications, fab audits, SPC, DOE, and FMEA activities while supporting process integration and production quality.

Own and improve wafer-level testing operations, including process development, qualification, production execution, process control, yield improvement, failure debugging, data analysis, documentation, and cycle-time optimization. Lead continuous improvement using DOE, SPC, Six Sigma, and root-cause analysis while collaborating with engineering, quality, supply chain, and manufacturing partners to support product qualification and production ramp.

Lead development, integration, optimization, and technical support for wafer bumping and Fan-Out processes used in silicon photonic chip wafers. Responsibilities include process pathfinding, materials qualification, reliability validation, failure analysis, yield improvement, SPC control, incoming wafer quality, and NPI documentation. The role requires hands-on advanced packaging experience and expertise in photolithography, deposition, electroplating, finite element analysis, DOE, FMEA, and analytical software.

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.

Provides L1/L2 desktop support for Windows and macOS, including device provisioning, troubleshooting, patching, onboarding, offboarding, asset management, and peripheral support. Assists with LAN, Wi-Fi, VPN, switching, and wireless access point operations. Administers Microsoft 365 and Entra ID accounts, licenses, groups, devices, compliance policies, MFA, and endpoint applications. Supports Intune, Azure, ITSM tools, security platforms, and basic PowerShell automation while coordinating escalations and maintaining technical documentation.

Provides first-line T1 and T2 helpdesk support across macOS, Windows, and Linux. Responsibilities include ticket triage, device imaging and deployment, onboarding and offboarding, identity administration, connectivity troubleshooting, hardware asset management, conference room AV support, and maintaining IT documentation. The intern will also collaborate on endpoint management, SaaS administration, identity access management, and security initiatives.