Jobs at Lumilens

Own strategic sourcing, supplier strategy, negotiations, cost optimization, supply continuity, and supplier performance for photonics products. Build and manage global supplier networks across silicon photonics, advanced packaging, optical components, contract manufacturing, and manufacturing partners. Partner with engineering, operations, manufacturing, and finance to support NPI, supplier qualification, capacity planning, risk mitigation, and transitions to high-volume manufacturing.

Lead global sourcing strategy and end-to-end supply chain management for optical and photonic components. Responsibilities include supplier identification and qualification, capacity and allocation planning, commercial negotiations, cost reduction, supply risk mitigation, dual-sourcing, supplier performance tracking, and cross-functional collaboration with engineering, quality, operations, program management, and contract manufacturing partners.

Lead development and optimization of wafer backside grinding, laser stealth dicing, and die sorting for silicon photonics. Troubleshoot process issues, improve yield and throughput, ensure compatibility with bumping/flip-chip, and produce SOPs, WIs, failure reports, and support NPI and process verification.

Develop and optimize optical alignment and assembly processes for photonic products from prototype through NPI and volume manufacturing. Responsibilities include active and passive alignment, epoxy dispensing and curing, equipment qualification, DOE, process characterization, statistical capability analysis, root-cause investigation, yield improvement, documentation, DFM/DFA support, and manufacturing transfer. The engineer will collaborate with R&D, manufacturing, suppliers, quality teams, and contract manufacturers to establish robust processes and production controls.

Manage external semiconductor foundry partnerships and coordinate technical, business, and production deliverables. Lead product transitions from NPI to high-volume manufacturing, improve on-time delivery and cycle time, and resolve yield, RMA, and process-excursion issues. Oversee root-cause analysis, corrective actions, quality metrics, process change notifications, fab audits, SPC, DOE, and FMEA activities while supporting process integration and production quality.

Own and improve wafer-level testing operations, including process development, qualification, production execution, process control, yield improvement, failure debugging, data analysis, documentation, and cycle-time optimization. Lead continuous improvement using DOE, SPC, Six Sigma, and root-cause analysis while collaborating with engineering, quality, supply chain, and manufacturing partners to support product qualification and production ramp.

Lead development, integration, optimization, and technical support for wafer bumping and Fan-Out processes used in silicon photonic chip wafers. Responsibilities include process pathfinding, materials qualification, reliability validation, failure analysis, yield improvement, SPC control, incoming wafer quality, and NPI documentation. The role requires hands-on advanced packaging experience and expertise in photolithography, deposition, electroplating, finite element analysis, DOE, FMEA, and analytical software.

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.

Provides L1/L2 desktop support for Windows and macOS, including device provisioning, troubleshooting, patching, onboarding, offboarding, asset management, and peripheral support. Assists with LAN, Wi-Fi, VPN, switching, and wireless access point operations. Administers Microsoft 365 and Entra ID accounts, licenses, groups, devices, compliance policies, MFA, and endpoint applications. Supports Intune, Azure, ITSM tools, security platforms, and basic PowerShell automation while coordinating escalations and maintaining technical documentation.

Provides first-line T1 and T2 helpdesk support across macOS, Windows, and Linux. Responsibilities include ticket triage, device imaging and deployment, onboarding and offboarding, identity administration, connectivity troubleshooting, hardware asset management, conference room AV support, and maintaining IT documentation. The intern will also collaborate on endpoint management, SaaS administration, identity access management, and security initiatives.

Build and own data pipelines, models, quality checks, dashboards, and visualizations for manufacturing and test data. Partner with optical, manufacturing, and quality engineers to create reliable data solutions, improve pipeline performance and cost, and support engineering and leadership decisions. Establish software engineering practices for data systems, guide technical direction across distributed sites, and mentor other engineers.

Owns strategy and execution for high-speed optical interconnect product lines, including co-packaged optics, 800G, and 1.6T transceiver platforms. Coordinates engineering, manufacturing, suppliers, quality, supply chain, sales, finance, and operations to drive product development, validation, launch readiness, customer adoption, and production transfer. Responsibilities include market and competitive analysis, customer engagement, technical trade-off evaluation, roadmap execution, risk management, business cases, and leadership reporting.

Lead development of packaged silicon photonics and optical interconnect products from requirements through validation and production. Define product requirements, analyze optical links, coordinate engineering and external partners, guide packaging and assembly execution, and establish testing strategies. The role requires hands-on laboratory work, customer and supplier engagement, cross-functional leadership, and attention to manufacturability, reliability, thermal performance, and scale-up readiness.

The Director of Silicon Test Engineering will lead test strategy and execution for silicon photonics products, optimizing test solutions and ensuring product reliability. Responsibilities include managing ATE test development, driving yield optimization, and collaborating with cross-functional teams while building a high-performing engineering team.

The role involves designing and optimizing advanced packaging solutions for ASICs, conducting FEA simulations, and collaborating with cross-functional teams to enhance photonics technologies for AI and high-performance computing.

As an IC Package FEA Engineer, you will conduct FEA simulations for advanced packaging solutions, optimize designs, and collaborate with cross-functional teams to enhance reliability and performance in photonic devices.

Lead software integration for high-speed optical transceivers on advanced switch architectures, ensuring automation and system debugging, collaborating with cross-functional teams.

The Failure Analysis Engineer leads investigations of optical, electrical, and mechanical failures, communicating insights to influence product design and improve manufacturing processes.

Lead development of wafer-level opto-electrical test solutions for NPO/CPO products across NPI to volume production. Design and qualify test hardware and software, manage RFQ and vendor qualification, transfer testers to production, create process documentation and training, and provide ongoing engineering support to maintain yield, throughput, alignment stability, and reliability.

Lead cross-functional programs across silicon, photonics, packaging, bring-up, validation, and system delivery. Create and execute project plans, manage risks and schedules, coordinate vendors and partners, and communicate status to leadership to drive product readiness on aggressive timelines.