Teams at Lumilens

Own and improve wafer-level testing operations, including process development, qualification, production execution, process control, yield improvement, failure debugging, data analysis, documentation, and cycle-time optimization. Lead continuous improvement using DOE, SPC, Six Sigma, and root-cause analysis while collaborating with engineering, quality, supply chain, and manufacturing partners to support product qualification and production ramp.

Lead development, integration, optimization, and technical support for wafer bumping and Fan-Out processes used in silicon photonic chip wafers. Responsibilities include process pathfinding, materials qualification, reliability validation, failure analysis, yield improvement, SPC control, incoming wafer quality, and NPI documentation. The role requires hands-on advanced packaging experience and expertise in photolithography, deposition, electroplating, finite element analysis, DOE, FMEA, and analytical software.

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.