Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers
Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.
Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.
Reliability & Stress Engineering: Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).
Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.
Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.
Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long-term process stability
Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.
Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.
Experience: 5+years of hands-on wafer bumping or Fan-out process integration or development experience, at OSAT or IDM internal advanced packaging line. Process exposure/experience on interposer, 2.5D/3D, chip on wafers on substrate, will be an added advantage.
Technical Knowledge:
Deep practical understanding of photolithography, wet etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD), moulding process adapted for backend bump fabrication.
Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.
Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.
Software Tools: High proficiency with robust analytical platforms like JMP, Minitab, or Python.
Skills Required
- Bachelor’s or Master’s degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline
- 5+ years of hands-on wafer bumping or Fan-Out process integration or development experience
- Experience at an OSAT or IDM internal advanced packaging line
- Practical understanding of photolithography, wet etching, CVD, PVD, and molding processes for backend bump fabrication
- Command of finite element simulation principles for warpage, thermal dissipation, and structural mechanical integrity
- Expertise with FMEA, SPC controls, and structured 8D problem-solving
- High proficiency with JMP, Minitab, or Python
- Process exposure to interposer, 2.5D/3D, or chip-on-wafer-on-substrate technologies
What We Do
Lumilens addresses the red hot market for AI data center infrastructure by designing, manufacturing and selling photonic interconnect solutions. We design and use custom robotics + AI in our factories to more efficiently build our products. Lumilens is backed by top-tier venture capital investors including Mayfield and Spark Capital.
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