Jobs at Ceva, Inc.

Develop and maintain automation scripts for front-end emulation and VLSI CAD flows. Support VLSI artifact execution and releases, improve infrastructure efficiency and tool integration, and manage version control and CI/CD pipelines for regression and build environments. Establish emulation methodologies and procedures while collaborating on VLSI, ASIC, design, and verification infrastructure.

Define end-to-end architectures for next-generation wireless radio subsystem platforms supporting Wi-Fi, Bluetooth, and UWB. Responsibilities include hardware/software partitioning, interfaces, multi-protocol operation, low-power optimization, security, testability, validation, system bring-up, and customer SoC integration. The role collaborates with RF, PHY, hardware, software, verification, and integration teams throughout product development and provides technical leadership in architecture decisions.

Develop AI and machine learning solutions for edge hardware and cloud inference. Research generative AI and LLM architectures, plan end-to-end network deployment, measure and improve model accuracy, and build hardware-aware quantization tools for a graph compiler. The role requires Python development, PyTorch, model evaluation, AI testing practices, and knowledge of common neural network architectures.

Develop and maintain SystemVerilog/UVM verification environments for Bluetooth, BLE, and IEEE 802.15.4 IP and subsystems. Define verification plans, build constrained-random tests, assertions, reusable components, and functional coverage. Integrate verification environments and verification IPs, debug RTL and testbench issues, and drive coverage closure. Collaborate with RTL designers, architects, integration teams, and cross-functional stakeholders while independently owning technical verification activities.

Design and own components of an AI graph compiler for NPU-based neural network and LLM execution. Develop memory management and data-movement systems, optimize performance, enable new NPU features, analyze bottlenecks, and collaborate with compiler and hardware architects on hardware-software solutions.

Execute the full formal verification cycle for DSP, AI processor, and hardware accelerator ASIC designs. Develop formal testbenches and SystemVerilog Assertions, define verification strategies and plans, collaborate with design and verification teams, track coverage and progress, and support verification completeness and final sign-off using industry-standard formal tools.

Develop and maintain embedded software for 5G modem systems, including hardware-block drivers. Analyze, debug, optimize, and verify code and test results, investigate complex hardware/software failures, improve performance and code size, integrate modules, and manage comprehensive test plans. The role also involves using AI tools to accelerate development and debugging.

Develop and maintain automation scripts for front-end emulation and VLSI CAD flows. Support VLSI artifact execution and releases, improve infrastructure efficiency and tool integration, and work with version control and CI/CD pipelines for regression and build environments. The role also involves establishing emulation methodologies and procedures. Candidates should be recent engineering graduates with Python, Linux or Unix shell scripting, and academic knowledge of VLSI, ASIC, and verification concepts.

Design and implement components of the AI Graph Compiler software for NPUs, optimizing performance under constraints and collaborating with architects and engineers.

The Digital Design Engineer will design and implement advanced Bluetooth solutions, manage project progress, and collaborate with cross-functional teams to ensure product performance and reliability.

Design and develop Ceva's open-source toolchain and graph compiler for DSP and NPU targets. Drive graph compilation flows, code generation, and optimizations. Integrate AI coding agents, own complex components end-to-end, mentor engineers, and collaborate with hardware, algorithm, and software teams globally.

Design and implement Ceva's AI Graph Compiler software stack for NPUs, optimizing performance and collaborating on hardware-software co-design while mentoring junior engineers.

Define and optimize system and PHY architecture for advanced wireless modem products. Collaborate with algorithm, HW/SW, RF and validation teams through design, integration, testing, and customer support, with focus on low-power implementations and productization.

Lead architecture, design and verification of Bluetooth and 802.15.4 MAC/PHY and SoC subsystems. Implement digital designs on FPGA for prototyping, support validation and certification, mentor engineers, track project progress, produce subsystem documentation, and drive process and tooling improvements.

Lead development of full VLSI verification flows for DSP ASICs: define verification strategy, micro-architecture tests, test plans, functional coverage, and build SystemVerilog-UVM/Specman environments. Use formal verification and emulation, collaborate across teams, and present results to management.