Jobs at Ceva, Inc.

Define and drive connectivity subsystem architectures (Wi‑Fi, Bluetooth, UWB) for SoCs, lead customer technical engagement, support tape-out, silicon bring-up, productization, cross-functional integration, and ensure production readiness.

Serve as technical lead bridging customers, FAEs, and global R&D to drive pre- and post-sales evaluations, integrations, debugging, optimization, and deployment of Ceva's NPU-based AI software and SDKs to achieve design wins and production readiness.

Design and implement Ceva's AI Graph Compiler software stack for NPUs, optimizing performance and collaborating on hardware-software co-design while mentoring junior engineers.

Maternity-leave HR role responsible for employee wellbeing, experience, internal communications, and employer branding. Plans and delivers events and engagement programs, manages vendors and budgets, produces internal content, coordinates global stakeholders, and supports cross-organizational projects to improve culture and belonging.

Lead architecture, design and verification of Bluetooth and 802.15.4 MAC/PHY and SoC subsystems. Implement digital designs on FPGA for prototyping, support validation and certification, mentor engineers, track project progress, produce subsystem documentation, and drive process and tooling improvements.

Develop and optimize embedded 5G modem software for uplink and downlink on Ceva DSPs and accelerators. Build and run tests on SW simulation, RTL, and FPGA; support customers and collaborate with VLSI and tools teams for performance and verification.

Lead development of full VLSI verification flows for DSP ASICs: define verification strategy, micro-architecture tests, test plans, functional coverage, and build SystemVerilog-UVM/Specman environments. Use formal verification and emulation, collaborate across teams, and present results to management.

Drive cross-functional business planning and operations for wireless, connectivity, and sensing business units. Lead pipeline, pricing, partnership strategy, contract lifecycle management, revenue forecasting, and P&L reporting while coordinating GMs, legal, finance, technical, and commercial teams to support growth and revenue objectives.

Entry-level role supporting VLSI CAD and emulation infrastructure: develop automation scripts, maintain CAD/emulation flows, work with version control and CI/CD, collaborate with global teams, and improve tool integration.

Customer-facing engineering role supporting Ceva's NPU and DSP hardware and architecture across pre-sales evaluation through post-sales integration. Maintain deep product expertise, create training materials and application notes, provide technical advice and support, and collaborate with R&D, field engineers, partners, and customers.

Customer-facing engineering role supporting Ceva's NPUs and DSPs hardware and architecture across the customer lifecycle. Maintain deep product expertise, produce training and documentation, provide pre- and post-sales technical support, and collaborate with R&D, FAE, partners, and customers on integration and evaluation.

Design and implement components of the AI Graph Compiler software for NPUs, optimizing performance under constraints and collaborating with architects and engineers.

The Digital Design Engineer will design and implement advanced Bluetooth solutions, manage project progress, and collaborate with cross-functional teams to ensure product performance and reliability.

Lead the development of software architecture for advanced neural network AI tools, collaborating with hardware/software teams to enhance NPU efficiencies and guide product innovation.

The R&D Technical Project Manager will lead multidisciplinary engineering teams in developing Neural Network Processor products, ensuring project delivery from planning through mass production, while managing technical risks and stakeholder communication.

Develop embedded software components for Bluetooth products, including design, implementation, testing, and collaboration with teams.

Design and verify high-end RF blocks for communication technologies, support system design, perform layout reviews, and engage in post-silicon verification.

Key contributor to AI Graph Compiler design for NPUs, optimizing performance under constraints, collaborating on HW-SW co-design, and mentoring junior engineers.

Manage all R&D projects at Mobile Broadband Business Unit involving VLSI architecture, design, algorithms, and software with up to 100 engineers.

Lead a team of 50 engineers in developing software tools for AI and Wireless platforms, ensuring high standards and collaboration with customers.