Jobs at Ceva, Inc.

Leads large-scale, multidisciplinary AI processor R&D programs from architecture through production and customer delivery. Coordinates hardware, algorithms, firmware, embedded software, toolchains, verification, and systems teams of 30+ engineers across global sites. Owns planning, schedules, risks, quality, KPIs, change control, PMO processes, customer communication, and executive reporting for NPU and edge AI products.

Lead digital verification activities from architecture definition through sign-off. Develop SystemVerilog and UVM verification environments, checkers, test benches, test plans, and functional coverage strategies for integrated AI hardware solutions. Troubleshoot complex issues, improve verification performance and quality, and collaborate across teams in an agile environment.

Supports global on-premises and cloud infrastructure, including physical and virtual servers, storage, networking, backups, monitoring, and recovery. Serves as the senior escalation point for enterprise systems, troubleshoots incidents, performs root-cause analysis, and drives infrastructure modernization, automation, high availability, and operational resilience across the organization.

Lead the architecture, RTL design, verification support, synthesis, and timing closure of advanced 5G baseband DSP cores and hardware accelerators. Optimize power, performance, and area while collaborating with algorithm, verification, backend, software, and customer teams through silicon bring-up. Develop programmable DSP architectures for multi-antenna and satellite connectivity systems.

Lead a team of senior system and algorithm engineers developing next-generation 5G modem products. Define modem systems, requirements, algorithms, and architectures from research through simulation and release. Collaborate with VLSI and software teams to balance performance, implementation cost, real-time constraints, and time-to-market. Maintain expertise in cellular standards, oversee MATLAB/C/C++/SystemC modeling, mentor engineers, and drive technical excellence.

Leads a team of front-end VLSI engineers developing AI processors, DSPs, and hardware accelerators. Owns architecture, design, validation, release, PPAA targets, design methodologies, signoff, and AI tool adoption. Collaborates with architecture, software, hardware simulator, CAD, and backend teams, while supporting system bring-up, debugging, and customer activities.

Lead a distributed backend engineering team while remaining hands-on with RTL-to-GDSII execution. Own synthesis, implementation, timing closure, physical verification, signoff, tapeout delivery, flow development, advanced-node bring-up, automation, and customer convergence across multiple complex projects. Mentor engineers, set priorities, resolve technical roadblocks, and collaborate with architecture, frontend, verification, and other stakeholders.

Develop and maintain automation scripts for front-end emulation and VLSI CAD flows. Support VLSI artifact execution and releases, improve infrastructure efficiency and tool integration, and manage version control and CI/CD pipelines for regression and build environments. Establish emulation methodologies and procedures while collaborating on VLSI, ASIC, design, and verification infrastructure.

Define end-to-end architectures for next-generation wireless radio subsystem platforms supporting Wi-Fi, Bluetooth, and UWB. Responsibilities include hardware/software partitioning, interfaces, multi-protocol operation, low-power optimization, security, testability, validation, system bring-up, and customer SoC integration. The role collaborates with RF, PHY, hardware, software, verification, and integration teams throughout product development and provides technical leadership in architecture decisions.

Develop AI and machine learning solutions for edge hardware and cloud inference. Research generative AI and LLM architectures, plan end-to-end network deployment, measure and improve model accuracy, and build hardware-aware quantization tools for a graph compiler. The role requires Python development, PyTorch, model evaluation, AI testing practices, and knowledge of common neural network architectures.

Develop and maintain SystemVerilog/UVM verification environments for Bluetooth, BLE, and IEEE 802.15.4 IP and subsystems. Define verification plans, build constrained-random tests, assertions, reusable components, and functional coverage. Integrate verification environments and verification IPs, debug RTL and testbench issues, and drive coverage closure. Collaborate with RTL designers, architects, integration teams, and cross-functional stakeholders while independently owning technical verification activities.

Execute the full formal verification cycle for DSP, AI processor, and hardware accelerator ASIC designs. Develop formal testbenches and SystemVerilog Assertions, define verification strategies and plans, collaborate with design and verification teams, track coverage and progress, and support verification completeness and final sign-off using industry-standard formal tools.

Develop and maintain embedded software for 5G modem systems, including hardware-block drivers. Analyze, debug, optimize, and verify code and test results, investigate complex hardware/software failures, improve performance and code size, integrate modules, and manage comprehensive test plans. The role also involves using AI tools to accelerate development and debugging.

Develop and maintain automation scripts for front-end emulation and VLSI CAD flows. Support VLSI artifact execution and releases, improve infrastructure efficiency and tool integration, and work with version control and CI/CD pipelines for regression and build environments. The role also involves establishing emulation methodologies and procedures. Candidates should be recent engineering graduates with Python, Linux or Unix shell scripting, and academic knowledge of VLSI, ASIC, and verification concepts.

Design and implement components of the AI Graph Compiler software for NPUs, optimizing performance under constraints and collaborating with architects and engineers.

The Digital Design Engineer will design and implement advanced Bluetooth solutions, manage project progress, and collaborate with cross-functional teams to ensure product performance and reliability.

Design and implement Ceva's AI Graph Compiler software stack for NPUs, optimizing performance and collaborating on hardware-software co-design while mentoring junior engineers.

Define and optimize system and PHY architecture for advanced wireless modem products. Collaborate with algorithm, HW/SW, RF and validation teams through design, integration, testing, and customer support, with focus on low-power implementations and productization.

Lead architecture, design and verification of Bluetooth and 802.15.4 MAC/PHY and SoC subsystems. Implement digital designs on FPGA for prototyping, support validation and certification, mentor engineers, track project progress, produce subsystem documentation, and drive process and tooling improvements.

Lead development of full VLSI verification flows for DSP ASICs: define verification strategy, micro-architecture tests, test plans, functional coverage, and build SystemVerilog-UVM/Specman environments. Use formal verification and emulation, collaborate across teams, and present results to management.