Teams at Ceva, Inc.

Execute the full formal verification cycle for DSP, AI processor, and hardware accelerator ASIC designs. Develop formal testbenches and SystemVerilog Assertions, define verification strategies and plans, collaborate with design and verification teams, track coverage and progress, and support verification completeness and final sign-off using industry-standard formal tools.

Develop and maintain embedded software for 5G modem systems, including hardware-block drivers. Analyze, debug, optimize, and verify code and test results, investigate complex hardware/software failures, improve performance and code size, integrate modules, and manage comprehensive test plans. The role also involves using AI tools to accelerate development and debugging.

Develop and maintain automation scripts for front-end emulation and VLSI CAD flows. Support VLSI artifact execution and releases, improve infrastructure efficiency and tool integration, and work with version control and CI/CD pipelines for regression and build environments. The role also involves establishing emulation methodologies and procedures. Candidates should be recent engineering graduates with Python, Linux or Unix shell scripting, and academic knowledge of VLSI, ASIC, and verification concepts.