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About the Business Unit:
Ceva develops state-of-the-art DSPs, AI processors, and hardware-accelerator IP for AI, vision, wireless, and base-station applications. Our VLSI organization transforms advanced architecture into production-ready silicon IP across leading technology nodes.
About the Role:
We are looking for an experienced physical-design leader who wants to remain close to technology while leading an accomplished engineering team.
You will lead a team of experienced backend engineers across Israel and India and own delivery across multiple projects in parallel.
This hands-on leadership role combines approximately 50% technical work and 50% team management, with end-to-end responsibility for turning complex RTL into tape out-ready GDSII.
Responsibilities:
Own and drive the complete RTL-to-GDSII flow, including synthesis, implementation, timing closure, physical verification, signoff, and tape out-ready IP delivery.
Lead, mentor, and develop a distributed team of experienced engineers while setting priorities and ensuring predictable, high-quality execution.
Provide hands-on leadership in flow development, advanced technology-node bring-up, integration, automation, and complex design closure.
Partner with architecture, frontend, verification, and other stakeholders to remove technical roadblocks and continuously improve backend methodologies.
The role includes working closely with customers and supporting backend convergence of the IP.
Requirements- B.Sc. or M.Sc. in Electrical Engineering
- At least 10 years of hands-on experience in VLSI backend or physical design
- Proven managerial or team-lead experience and the ability to guide a highly experienced engineering team.
- Deep knowledge of synthesis, place and route (P&R), static timing analysis (STA), physical verification, and signoff flows.
- Proven ownership of complete RTL-to-GDSII execution for complex designs, including advanced process technologies of 7nm and below.
- Strong TCL and Python scripting skills, together with excellent troubleshooting, communication, prioritization, and collaboration capabilities.
Advantages:
- Top-level integration experience for a multi-partition SoC.
- Strong understanding of RTL design using Verilog or SystemVerilog.
- Experience developing physical-design flows, infrastructure, or advanced-node methodologies.
Skills Required
- B.Sc. or M.Sc. degree in Electrical Engineering
- At least 10 years of hands-on experience in VLSI backend or physical design
- Managerial or team-lead experience guiding experienced engineering teams
- Deep knowledge of synthesis, place and route, static timing analysis, physical verification, and signoff flows
- Experience owning complete RTL-to-GDSII execution for complex designs
- Experience with advanced process technologies of 7nm and below
- Strong TCL and Python scripting skills
- Excellent troubleshooting, communication, prioritization, and collaboration skills
- Top-level integration experience for a multi-partition SoC
- Strong understanding of RTL design using Verilog or SystemVerilog
- Experience developing physical-design flows, infrastructure, or advanced-node methodologies
What We Do
Ceva powers the Smart Edge, bridging the digital and physical worlds to bring AI-driven products to life. Our Ceva AI fabric portfolio of silicon and software IP enables devices to Connect, Sense, and Infer – the essential capabilities for the intelligent edge. From 5G, cellular IoT, Bluetooth, Wi-Fi, and UWB connectivity to scalable Edge AI NPUs, AI DSPs, sensor fusion processors and embedded software, Ceva provides the foundational IP for devices that connect, understand their environment, and act in real time. With more than 20 billion devices shipped and trusted by 400+ customers worldwide, Ceva is the backbone of today’s most advanced smart edge products – from AI-infused wearables and IoT devices to autonomous vehicles and 5G infrastructure. Our differentiated solutions deliver seamless integration into existing design flows, total flexibility to combine solutions based on design needs and ultra–low–power performance in minimal silicon footprint, helping customers accelerate development, reduce risk, and bring innovative products to market faster. As technology evolves toward Physical AI, Ceva’s IP portfolio lays the foundation for systems that are always connected, contextually aware, and capable of intelligent, real-time decision-making.
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