Senior Digital Design Verification Engineer - Hardware

Posted Yesterday
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Santa Clara, CA, USA
In-Office
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The Role
Develop and execute verification plans for SerDes digital designs using SystemVerilog, UVM, simulation, and Cadence Palladium emulation. Build verification environments, regressions, models, stimulus generators, checkers, and test infrastructure in C/C++. Debug RTL, emulation, simulation, and RNM failures; analyze coverage; and collaborate with architects and design teams to deliver high-quality IP.
Summary Generated by Built In

We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join our diverse team today!


As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a best-in-class team that delivers IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols!


What you’ll be doing:

  • Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
  • Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long-duration system scenarios. Run regressions, debug and triage failures, and reproduce issues in simulation when needed to support root-cause analysis and resolution.
  • Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.
  • Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
  • Work with architects, digital and analog designers, and pre- and post-silicon verification teams to define verification scope, close coverage, and deliver high-quality IP on schedule.

What we need to see:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
  • At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level.
  • Hands-on experience with Cadence Palladium or a comparable hardware emulation platform, including environment bring-up, regression execution, failure triage, and debug.
  • Strong C/C++ programming skills, with experience developing verification models, test infrastructure, or hardware validation tests.
  • Strong SystemVerilog skills and experience building verification environments using UVM.
  • Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure.
  • Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation.

Ways to stand out from the crowd:

  • Direct experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium.
  • Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation.
  • Experience developing SerDes RNM models and correlating their behavior with analog simulation results or silicon measurements.
  • Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training.
  • Expertise in high-speed protocols such as PCI Express, USB, or SATA.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 10, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Skills Required

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience
  • At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level
  • Hands-on experience with Cadence Palladium or a comparable hardware emulation platform
  • Strong C/C++ programming skills and experience developing verification models, test infrastructure, or hardware validation tests
  • Strong SystemVerilog skills and experience building verification environments using UVM
  • Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure
  • Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation
  • Experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium
  • Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation
  • Experience developing SerDes RNM models and correlating behavior with analog simulation results or silicon measurements
  • Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training
  • Expertise in high-speed protocols such as PCI Express, USB, or SATA

NVIDIA Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about NVIDIA and has not been reviewed or approved by NVIDIA.

  • Equity Value & Accessibility — Feedback suggests equity grants, stock options/RSUs, and a discounted ESPP materially boost total compensation and can deliver significant wealth-building when the stock performs well.
  • Healthcare Strength — Feedback suggests medical, dental, and vision plans with in-network preventive care at 100%, telehealth, and concierge-style support are comprehensive and valued.
  • Parental & Family Support — Feedback suggests up to 22 weeks fully paid parental leave, fertility coverage, and adoption/surrogacy reimbursement provide strong family-focused benefits.

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The Company
HQ: Santa Clara, CA
21,960 Employees
Year Founded: 1993

What We Do

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, NVIDIA is increasingly known as “the AI computing company.”

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