About the team and organization
Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies.
As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.
Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Master's degree in Electrical Engineering or a related discipline and at least 5+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field.
- 3+ years of hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
- Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
- Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling.
- Experience developing LLE models for FinFET or GAAFET technologies.
- Skilled in Python scripting for automation and documentation.
Preferred Qualifications
- Ph.D. in Electrical Engineering or a related discipline with 8+ years of industry experience in the semiconductor field.
- Deep expertise in compact modeling, including one or more of the following areas:
- Layout-dependent effects (LDE) and their impact on circuit performance.
- Modeling using Open Model Interface (OMI)
- Strong understanding of process flow, layout, and basic circuit design/simulation.
- Modeling self-heating effects and their influence on device and circuit performance.
- Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
- o Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
- Experience with machine learning algorithms and their application is data analysis and compact model development.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Master's degree in Electrical Engineering or a related discipline and at least 5 years of semiconductor industry experience
- Alternatively, Ph.D. in Electrical Engineering or a related discipline with at least 3 years of semiconductor industry experience
- At least 3 years of hands-on experience with BSIM-CMG and other compact transistor models at advanced nodes
- Proficiency with extraction tools such as ICCAP or MBP and commercial simulators such as HSPICE or Spectre
- Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling
- Experience developing LLE models for FinFET or GAAFET technologies
- Proficiency in Python scripting for automation and documentation
- Ph.D. in Electrical Engineering or a related discipline with 8 or more years of semiconductor industry experience
- Expertise in layout-dependent effects and their impact on circuit performance
- Experience using Open Model Interface (OMI)
- Understanding of semiconductor process flow, layout, and basic circuit design and simulation
- Experience modeling self-heating effects and their influence on device and circuit performance
- Experience developing device-targeting and benchmarking methodologies, including corners and statistical variation models
- Technical leadership experience and ability to collaborate across multiple teams and geographies
- Experience applying machine learning algorithms to data analysis and compact model development
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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