About the Team
The Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services that allow internal and external customers to bring winning products to the marketplace. Your work will directly enable design teams to get to market faster with leadership products based on innovative technologies.
As a member of CDMG, you will be at the forefront of co-optimizing Intel's state-of-the-art process technology, enabling customers with diverse design needs to deliver best-in-class products for data-centric applications.
As a Semiconductor Device Modeling Engineer, you will be responsible for characterizing device behavior and generating/updating device models for new technologies while ensuring robust and accurate model simulations.
Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Master's degree in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field; OR
- PhD in Electrical Engineering or a related discipline with a minimum of 1 year of industry or research experience and a dissertation focused on semiconductor devices or processes.
- Hands-on experience in Python or C, Shell programming.
- Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.
- The ability to work independently after the initial ramp-up time.
Preferred Qualifications:
- A Ph.D. degree in electrical engineering or related discipline with 3 + years of industry experience in the semiconductor field.
- Experience in BSIM models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators. (example: HSPICE, SPECTRE, etc.)
- Understanding of corner, statistical and sub-circuit models and their usages.
- Understanding of layout effects and models.
- Understanding of basic analog and digital circuit blocks and model interaction.
- Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems. Experience in test automation and RF/noise/reliability tests is a plus.
- Understanding of Aging Simulations and reliability methodologies and tools is a plus.
- Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Master's in Electrical Engineering or related plus 3+ years industry experience OR PhD in EE or related with 1+ year industry/research and dissertation focused on semiconductor devices or processes.
- Hands-on experience in Python or C, and Shell programming.
- Experience or coursework in semiconductor device physics, process flow, layout, and circuit design and simulation.
- Ability to work independently after initial ramp-up.
- PhD in EE or related with 3+ years industry experience.
- Experience with BSIM and other compact models, extraction tools (ICCAP or MBP), and simulators (HSPICE, SPECTRE).
- Understanding of corner, statistical and sub-circuit models and their usages.
- Understanding of layout effects and models.
- Understanding of basic analog and digital circuit blocks and model interaction.
- Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems; test automation and RF/noise/reliability tests a plus.
- Understanding of aging simulations and reliability methodologies and tools.
- Experience in Cadence design environment including schematic capture, Virtuoso layout design, DRC, LVS, and layout extraction.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
-
Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
-
Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
-
Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
