The E-Core CPU Layout Design Engineer will drive physical design implementations, work with circuit engineers, debug tools, and ensure project alignment across teams, requiring strong problem-solving skills.

Develop firmware for DDR memory subsystems, ensure performance and reliability, and collaborate on architecture and debugging for innovative memory solutions.

Responsible for timing analysis and optimization of SoCs, including generating timing constraints, fixing violations, and collaborating on clock network design.

Develop custom circuit designs for Intel's next-generation CPU programs, ensuring high-performance and low-power design through various circuit activities and validation methods.

The IP Design Verification Engineer ensures functional integrity of IP designs through verification, test bench development, and collaboration with various teams.

Design and deliver high-performance CPU blocks for manufacturing, leading verification and sign-off while mentoring junior engineers and optimizing designs.

This role involves verifying SoC functionality, developing test plans and environments, executing tests, debugging issues, and collaborating with design teams.

The role involves developing physical layout verification software, ESD protection verification, and extraction techniques to support Intel's advanced process technologies. Collaboration with multiple teams and EDA vendors is essential, along with coding in various programming languages and utilizing EDA tools.

This role involves developing and delivering high-quality technology collaterals and EDA tools for Intel's advanced process technologies, focusing on runset development, ESD verification, and extraction solutions.

Responsible for deploying, configuring, and managing Linux OS environments, particularly RHEL, and layered applications while ensuring security and performance.

The Accounting Technical Specialist supports statutory audits, compliance with accounting standards, manages financial filings, and drives operational excellence in financial processes.

The Compiler Engineer will enhance and maintain the Intel Fortran compiler, develop new features, and support team collaboration, while resolving customer inquiries.

Develops logic design and RTL coding for graphics IPs, optimizing for power and performance, ensuring correct integration in full chip designs.

The Senior AI SoC Architect will lead the design and development of AI SoCs, influence architectural direction, and collaborate across teams for innovation in technology.

The Compiler Engineer will develop and advance an open-source compiler stack, focusing on language extensions and optimizing performance for AI and HPC workloads. Collaboration with global teams to ensure integration and reliability is key.

The role involves designing wireless communication systems, optimizing HW/SW integration, leading cross-functional teams, and authoring technical documentation.

Participate in FIP Integration QA work, utilize industry standard tools for design, perform SoC design flow, script for automation, and collaborate with internal teams and vendors for quality assurance.

Responsible for defining and validating SoC IP blocks, collaborating with teams to ensure quality silicon for AI applications, and mentoring junior engineers.

The role involves driving SoC/ASIC verification, mentoring junior engineers, and enhancing verification methodologies for complex mixed signal designs.

As a Physical Design Engineer, you'll support FIP Integration QA, develop reference designs, perform QA flows, and optimize processes using AI/ML techniques.