Jobs at Intel

Lead the strategy and roadmap for Intel's global web presence, driving AI-first discovery, personalization, and measurable growth. Align cross-functional teams (design, content, engineering, SEO, analytics), manage agencies, influence senior stakeholders, and turn strategy into delivered experiences while refining measurement and embedding AI to increase throughput and impact.

Measure, analyze, and debug SoC/CPU and platform power and performance on a rail-by-rail basis. Produce projections/estimates, create Power Performance Guide collateral, bring up test platforms, and align with internal teams and OEMs to close power/performance gaps.

Measure, analyze, and debug power and performance of Intel notebook and desktop SoC/CPU platforms. Create rail-by-rail power measurements, develop projections/estimates, align with engineering and marketing teams, publish Power Performance Guide collateral, and bring up test platforms for calibration and measurement to support product launches.

Design and execute verification plans and UVM-based testbenches to validate CPU logic against architectural specs. Perform functional coverage analysis, system-level simulation, debug pre-silicon issues, automate verification with scripts, collaborate with architects and RTL teams, and maintain verification infrastructure and documentation.

Join the SoC performance architecture team to enhance power and performance modeling for client products, collaborating on micro-architecture solutions and handling complex SoC performance analysis.

Lead substrate development and ramp activities to optimize supply chain, quality, yield, and cost. Define inspection methodologies, run root-cause analysis, drive supplier selection and validation, establish control standards and KPIs, and implement remediation with suppliers and cross-functional teams. Benchmark emerging technologies and align roadmap gaps between manufacturing capability and market demands.

Design, simulate, validate, and debug signal integrity for high-speed boards, packages, and SerDes links. Perform interconnect modeling, correlate simulations with bench measurements, create implementation guidelines, run conformance tests, and collaborate with IP and silicon teams to meet product requirements for Ethernet and PCIe networking solutions.

Lead engineering teams building analyzers and debuggers (e.g., Intel System Debugger, VTune) to enable observability, profiling, and performance analysis. Define strategy, collaborate across HW/SW, drive technical excellence, mentor engineers, and deliver products for AI/HPC and developer communities.

Drive end-to-end verification for SoC/IP blocks: create verification plans, architect UVM testbenches, develop constrained-random and directed tests, close functional/code coverage, debug in simulation/emulation, integrate VIPs, leverage assertions/formal, and collaborate across design, firmware, and validation to achieve signoff and high-quality silicon.

Design, develop, and maintain decision-support applications for manufacturing and supply chain. Analyze business requirements, design data architecture and interfaces, implement UIs, develop data quality monitors, optimize database performance, and support users to resolve data and system issues. Monitor application health for usability, scalability, and performance improvements.

The Compiler Engineer will design, develop, and maintain Intel's LLVM-based compiler stack, collaborating with hardware teams and contributing to Clang and SYCL technologies, ensuring optimal compiler performance for AI and HPC applications.

Designs and implements CPU RTL, performs RTL coding and simulation, optimizes logic for power/performance/area/timing, documents microarchitectural specs, reviews verification, fixes failing RTL tests, and supports SoC integration and customers.

Develop, maintain, and support tools, flows, and methodologies for post-silicon power, thermal, and performance analysis. Collaborate on design and implementation, ensure software reliability via testing and CI/CD, and improve existing processes and tooling.

Develop and execute verification plans and scalable UVM/SystemVerilog testbenches to validate CPU logic against architecture. Run system-level simulations, debug pre-silicon issues, collaborate with architects and RTL designers, maintain verification infrastructure, and document strategies while contributing to microarchitecture feature definition.

Develop and execute IP verification plans, design and maintain test benches and simulation models, debug presilicon issues, collaborate with architects/RTL/physical design teams, and improve verification infrastructure and methodologies.

Support capitalization process for front-end and back-end foundry activities, drive month-end close and reporting, build financial workflows and automation, perform variance root-cause analysis, evaluate capex and financing, and deliver ad hoc KPI and decision-support analysis.

Design and implement CPU logic and RTL, participate in architecture/microarchitecture, optimize for power/performance/area/timing, write/verify RTL, document microarchitectural specs, and support SoC integration and customers.

Develop long-term capacity strategies and production capacity models for foundry operations. Analyze operational data, optimize equipment schedules and layouts, forecast build plans, and collaborate cross-functionally to improve factory efficiency, reduce cost, and support capital and capacity decisions.

Develop and implement reference designs using Foundational IP, execute full SoC physical design flow from RTL to GDS, run IP QA flows, script and automate design/debug flows, build IP-level quality checks, collaborate with EDA vendors and internal IP teams, and apply data analytics/AI-ML to improve processes and quality.

Validate and QA Intel PDKs across process nodes and EDA flows by developing and running regression test suites, creating layout and circuit test cases, automating regressions, debugging failures, and performing pre- and post-layout simulations and parasitic extraction comparisons.