Jobs at Intel

The Semiconductor Manufacturing Engineer provides operational support for high volume fabrication facilities, optimizing processes, defining requirements, and collaborating with stakeholders to enhance manufacturing efficiency.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

The role involves analyzing user information, documenting business processes, training users, supporting testing, and managing data configurations with Windchill PLM.

The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.

Develop and sustain integrated defect monitors for semiconductor processes. Own multiple monitors, analyze data statistically (e.g., JMP), troubleshoot complex issues, optimize tool performance and recipes, and lead continuous improvement to improve yields and prevent defect recurrence.

Lead design and define optical subsystem architecture for next-generation data centers, optimizing bandwidth, latency, power, and cost. Translate customer requirements into system and product specs, evaluate protocols and PHY components, build analytic performance models, and validate via simulation. Collaborate across CPU, interconnect, and software teams, guide vendors, drive R&D and mentor engineers on co-packaged optics and photonic integration.

Responsible for designing and optimizing power and performance plans for IPs and SoCs, driving recommendations for architectures, and ensuring performance/power balance. Requires strong communication skills for cross-functional collaboration.

Manufacturing Operators perform product manufacturing and assembly tasks, support new product development, optimize production efficiency, and maintain quality standards.

The CPU Memory Design Engineer will design and develop custom memories and digital circuits for Intel CPUs, focusing on low-power and high-performance memory designs.

Design and develop custom and compiler-based memory circuits including SRAMs and caches, focusing on high-performance and low-power implementations.

Lead a team to develop and deliver analog and mixed-signal IP (ADCs, DACs, PLLs, TX/RX, regulators, clocking). Drive architecture, design, verification, silicon bring-up, validation, and production readiness. Manage schedules, resources, and cross-functional collaboration while building and mentoring engineering talent and influencing technical roadmaps.

Optimize and maintain inline defect metrology and yield systems for semiconductor manufacturing. Develop data pipelines, statistical analyses, visualizations, ML models, and algorithms to transform fab and defect data into actionable yield improvements. Support new product introductions, harden equipment systems for production, and collaborate with equipment, automation, and manufacturing teams to ensure data integrity and manufacturability.

Design and optimize semiconductor packaging processes and equipment; apply DOE/SPC and statistical methods; design test equipment for environmental and mechanical stress; ensure manufacturability and material specifications; collaborate with suppliers; lead problem-solving and continuous improvement; standardize qualification and quality systems.

Lead pre-silicon functional verification of Atom CPU cores: develop verification plans, SystemVerilog/UVM testbenches, run system-level simulations, debug RTL/microarchitecture issues, collaborate with architects and design teams, and improve verification infrastructure and automation to ensure correctness, performance, and power-efficiency before first silicon.

Lead end-to-end strategic foundry customer programs, acting as primary customer interface, coordinating cross-functional teams (product, engineering, supply chain, manufacturing), driving schedule/cost/quality outcomes, mitigating risks, and establishing governance, reporting, and continuous improvement from engagement through production ramp and EOL.

Develop and prototype software and modeling solutions for factory automation. Perform discrete event simulation, statistical analysis, and modeling to solve manufacturing and stochastic systems problems. Collaborate with cross-functional teams and industry partners to validate ideas and drive manufacturing roadmap improvements.

Lead architecture of RDMA transports and datacenter fabrics for large-scale AI, cloud, and HPC. Define transport protocols, congestion and flow control, reliability, and collective communication optimizations across silicon, firmware, and software to improve cluster performance and scalability.

Develop and optimize software applications, algorithms, and AI solutions; formulate linear and integer optimization models using CPLEX/OPL, AMPL, or Gurobi; prototype solutions, scale and decompose large MIP/CP models, perform code reviews, and analyze/visualize data while collaborating cross-functionally.

Lead physical design for neuromorphic silicon: architect floorplans, define timing/power constraints, run synthesis/place-and-route, debug timing/EM/IR/LVS/DRC, run back-annotated simulations, script and automate EDA flows, and drive block- and chip-level closure to meet power, performance, and area targets.

Design and implement CPU RTL for integer, floating point, and reservation station logic. Drive RTL coding, simulation, and optimization for power, performance, area, and timing. Participate in architecture definition, review verification plans, resolve RTL test failures, and provide technical leadership and cross-team collaboration to deliver CPU IP for full-chip integration.