Jobs at Intel

Lead development and integration of timing-closure flows for advanced APR, drive AI-agent usage for RTL-to-GDS workflows, run DTCO experiments across PPA objectives, coordinate with foundry and EDA vendors to debug non-determinism, and define deterministic PPA measurement for TFM releases.

Design and implement CPU core RTL features from architect specs, create microarchitectural specs, optimize RTL for power/performance/area/timing, collaborate with validation and back-end teams, and drive design decisions and forums.

Perform RTL-to-GDS physical design implementation for custom IP and SoC: synthesis, floorplanning, place-and-route, CTS, STA, power/clock distribution, reliability and power/noise analysis, verification and signoff (formal, LVS/ERC/DRC, power integrity), timing closure, DFT, and methodology/flow automation.

Perform block-level physical design of Hard-IPs and testchips from netlist to GDSII: floorplanning, power intent, placement, CTS, routing, optimization, ECO closure, verification (DRC/LVS, ICV), QoR improvements, scripting/automation, and cross-team collaboration to meet sign-off quality gates.

Drive physical implementation of Atom CPU layouts: build and verify cell-to-top-level layouts, implement memory compilers and custom IP, collaborate with circuit designers and CAD teams, and align with SoC groups to ensure reuse and consistency.

The NPI Integrator will lead new product/process introduction, coordinating documentation, tracking processes, and ensuring product compliance through development cycles.

The Physical Design Timing Engineer will perform SOC level timing analysis, ensuring designs meet performance and functionality requirements, collaborating with various teams to optimize solutions.

The job entails managing factory operations, implementing automation solutions, conducting cost studies, and collaborating on process improvements with cross-functional teams.

As a Senior Formal Verification Engineer, you will develop verification strategies and environments for AI SoCs, ensuring the correctness of digital designs through formal verification methods and collaboration with engineering teams.

The Senior Pre-Silicon Verification Engineer will develop verification strategies for mixed-signal designs, execute plans, and collaborate with teams to ensure functional compliance before fabrication.

Build and maintain bottom-up wafer demand models for assigned markets, analyze competitive dynamics and process node trends, author market analyses and white papers, and provide strategic recommendations to Intel Foundry while collaborating with external analysts and stakeholders.

Develop algorithms and software for image processing and analysis, manage tests, troubleshoot performance issues, and document software changes in a semiconductor manufacturing environment.

Lead business development and sales for Intel Foundry Services, managing sales plans, customer relationships, and negotiating contracts. Develop strategies to drive revenue and ensure customer satisfaction.

Develop and maintain MSVC compiler backend optimizers and code generation for Intel architectures. Drive performance improvements, collaborate with hardware architects, validate correctness via benchmarking and profiling, resolve performance bottlenecks, incorporate research advances, and mentor junior engineers.

The role involves providing technical support for Intel Ethernet products, collaborating on solutions, managing customer feedback, and evaluating tools to enhance performance in networking solutions.

The Sales Operations Analyst enhances sales operations at Intel by managing data processes, optimizing supply and revenue strategies, and improving decision-making through analytics and business intelligence.

The Test Module Engineer oversees high-volume equipment for IC manufacturing, driving process improvements and ensuring quality. Responsibilities include maintenance, data analysis, and technology transfer across global teams.

The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.

Lead market intelligence for foundry end markets by building and maintaining bottom-up wafer demand models, analyzing competitive dynamics, authoring white papers, and providing strategic recommendations. Coordinate with external analysts, manage analyst teams, and deliver insights using advanced Excel and Power BI under tight deadlines.

The role involves physical design implementation of custom CPU designs, including synthesis, static timing analysis, verification, and collaborating to optimize CPU parameters. Leadership and communication skills are essential.