Jobs at Intel

Validate mixed-signal IPs by developing verification plans, testbenches, and simulation models; execute simulations, analyze power/timing, debug and perform root-cause analysis; collaborate with architects, RTL and physical design teams; lead review of test plans and improve verification methodologies and tools.

Operate, monitor, and maintain high-volume semiconductor manufacturing equipment; conduct tests and measurements; identify and implement process improvements; perform maintenance and repairs; collaborate with suppliers and global teams for transfers, training, and audits; manage equipment installation, conversion, and qualification to support production ramp-up and yield optimization.

Configure, customize and implement SAP ECC/S4 HANA Material Management and SAP Ariba solutions; translate business requirements, deliver backlog features in Agile teams, perform testing and automation, and act as L3 production support and root-cause SME for procurement processes.

Drive procurement and sourcing technology products: define vision and roadmap, create/prioritize user stories and backlog, participate in scrum ceremonies, collaborate with stakeholders and delivery teams, support production as Level 3 SME and lead problem resolution for SAP S/4HANA and SAP Ariba solutions.

Support and optimize Intel's global supply chain by implementing process and quality improvements, defining inspection methodologies, monitoring supply-demand trends, driving supplier performance, leading failure analyses, and developing specifications to reduce variability and risk.

Design, develop, and simulate analog and mixed-signal circuits for advanced process nodes. Create floorplans, extract parameters, run tests, verify performance/power/area/timing/yield, and collaborate with architecture and layout teams to resolve design challenges and drive continuous improvement.

Design, develop, integrate, test, validate, and debug software across the Linux stack including drivers, kernel, frameworks, and applications. Work on Bluetooth software and tools, USB/PCIe protocols, Linux porting, backporting/upstreaming, and maintain codebases to ensure high code quality.

Support monthly and year-end payroll accounting activities including journal entries, reconciliations, audit support, balance sheet reconciliations, process documentation, and cross-functional collaboration to improve automation and efficiency.

The role involves developing layout design methodologies, integrating full-chip SoC designs, collaborating with various teams, and ensuring scalable solutions for testchip platforms.

Lead PCB layout design for rigid and flexible boards using Cadence Allegro; manage CAD tools, part libraries, DFx packages, contractors, and license needs. Deliver high-density, high-speed, mixed-signal PCB designs from feasibility to tape-out while coordinating with electrical, mechanical, thermal, and manufacturing teams.

Design and verify complex analog circuit layouts, perform microfloor planning and power/grid/ESD verification, troubleshoot tools and flows, and collaborate with circuit and structural teams to optimize area, power, reliability, and performance.

Responsible for verifying CPU logic designs using advanced methodologies, developing verification plans, and collaborating with design teams to ensure correctness and performance.

As an IP Logic Design Engineer, you will design and validate high-performance IP blocks, collaborate with stakeholders, and ensure quality delivery for SoC integration.

Develop, validate and maintain software components and tools for Intel Edge platforms. Deploy and debug Intel Edge software, design and optimize AI (visual analytics, generative and physical AI) applications, resolve Linux installation issues, provide sample code and demos, optimize AI pipelines for CPUs/GPUs/NPUs, support APJ customers, and analyze benchmarking results against competitors.

Develop, validate, and maintain software components and tools for Intel Edge platforms; deploy/debug Intel Edge software; design and optimize AI (visual analytics, GenAI, physical AI) applications; troubleshoot Linux installations; provide sample code, demos, technical guidance, and customer support across APJ; analyze AI benchmark reports and compare competitor offerings.

Design, develop, and optimize algorithms for oneDNN targeting Intel processors and graphics. Conduct performance analysis and contribute to low-level tuning and optimization efforts, collaborating with cross-functional teams and engaging with the open-source community.

Develop mixed signal and high-speed IPs by writing RTL code, performing simulations, optimizing designs, and supporting SoC customers for high-quality integration.

Manage and optimize high-volume semiconductor manufacturing equipment and processes. Improve production efficiency, lead equipment installation/qualification during factory ramps, support maintenance and repairs, drive continuous improvement, transfer technology across sites, and ensure safety, quality, and yield targets are met.

Perform RTL-to-GDS physical design for custom IP and SoC: synthesis, place-and-route, CTS, STA, power/noise and reliability analysis, verification/signoff (FEV, LVS/DRC, power integrity), optimize power/frequency/area, and improve automation/methodologies.

The IP Design Verification Engineer will validate IP designs for SoC applications, develop test benches, and ensure compliance with DDR protocols. Responsibilities include RTL validation, creating test plans, executing tests, and automating validation processes while collaborating with cross-functional teams.