Jobs at Intel

Design and optimize analog and mixed-signal circuits (power delivery, IPs) for advanced CMOS nodes. Perform circuit simulation, floor-planning, post-layout extraction, verification, and validation. Collaborate with architecture, layout, and validation teams, analyze test data, and iterate designs to meet power, performance, area, timing, yield, and robustness goals.

Drive SoC performance architecture for client products: research and improve performance modeling methodologies, model microarchitecture ideas, analyze bottlenecks, propose solutions, and collaborate with design and validation teams to productize performance features.

Support and improve automated wafer test processes for CPU/SOC products: investigate and debug test platform failures across electrical/process/mechanical/optical/SW, perform data mining and statistical analysis, develop scripts and test optimizations, coach technicians, manage spares and equipment availability, and lead new-product test readiness and cross-site improvements.

Design, develop, and optimize oneCCL communication library features for low-latency, high-throughput HPC workloads. Collaborate with scientists and hardware teams on Aurora supercomputer integrations, implement and enhance communication protocols, benchmark and analyze performance across configurations, and debug complex cross-layer hardware/software issues.

Design, implement, and optimize distributed LLM inference systems and framework components. Implement distributed algorithms, schedulers, KV cache management, and communication layers. Profile workloads to find bottlenecks, collaborate to improve latency, throughput, scalability, and contribute code, tests, and documentation to internal and open-source projects.

Provide technical accounting advice and drive compliance and process transformation for global legal entities. Ensure accurate valuation, statutory reporting, US GAAP/IFRS/Local GAAP treatments, support SAP S4 design, lead stakeholder relationships, and manage entity restructurings, liquidations, and continuous improvement projects.

Lead end-to-end NPI and technology transfer for assembly and test, owning program plans, governance, cross-functional alignment, risk management, manufacturing readiness, ramp to volume, and continuous improvement to meet launch and customer commitments.

Lead design and development of advanced manufacturing test processes and equipment for post-packaging Burn In, Final Test and System Test. Collaborate with cross-functional teams and suppliers, perform process characterization, optimization and equipment metrology, recommend process and cost improvements, and implement new test technologies.

Lead product strategy and roadmap for Ethernet networking products across cloud, enterprise, and service provider markets. Gather and prioritize customer requirements, drive market and competitive analysis, build business cases and pricing, partner with engineering, sales, and marketing for go-to-market, and engage strategic customers and industry forums to influence product lifecycle and adoption.

Develop and execute verification testbenches and RTL models for Power Management Controller IP. Define test plans, create tests and tools, debug RTL and platform issues, collaborate across teams and partners, and validate new architectural features using simulation and firmware co-validation environments.

Enterprise-focused Account Executive responsible for building C-suite relationships, driving Intel-powered solution sales, collaborating with OEMs and partners, executing account plans, and meeting revenue and forecast goals. Advocates for customers internally, identifies upsell/cross-sell opportunities, and supports joint marketing and recovery plans to improve customer experience.

Design and develop analog and mixed-signal circuits for high-speed IO (memory PHYs). Perform transistor-level design, simulation, layout reviews, post-silicon validation, and collaborate cross-functionally to meet power, performance, area, timing, and yield targets.

Lead physical design and implementation of CPU core blocks from RTL to GDS: synthesis, floorplanning, place-and-route, STA, power and physical verification, PPA convergence, debug, automation, and cross-team collaboration while mentoring junior engineers.

Design and verify cell, block, and full-chip layouts using floorplanning, schematic-to-layout verification, parasitic extraction, and place-and-route techniques. Debug reliability issues, perform custom polygon edits, and execute full-chip assembly and verification. Coordinate project staffing and schedules while improving methodologies and meeting quality and timeline goals.

Implement block-level physical design for CPU cores: synthesis, floorplanning, place-and-route, STA, power and physical verification. Debug timing, power, and DRC/LVS issues, develop automation scripts (TCL/Python), collaborate with RTL/clocking/full-chip teams, and improve design flows to meet PPA targets.

Sustain automotive and client semiconductor products in high-volume manufacturing. Drive product sustaining strategies to meet quality and cost targets, reduce SBL triggers, perform risk assessments, ensure burn-in coverage, interface with foundry/OSAT partners, analyze customer returns and early feedback, monitor post-silicon quality, and implement improvements into future designs and processes.

Perform functional verification and emulation validation of server SoCs and IPs. Develop scalable verification plans, testbenches, and environments (UVM/SV), execute simulations and emulation runs, debug pre-silicon issues, collaborate with architects and RTL teams, drive coverage closure, incorporate security tests, and improve verification infrastructure based on post-silicon learnings.

Design and deliver full-custom and compiler-based SRAMs, ROMs, custom memories, large multi-ported register files and caches for Intel CPUs/SoCs. Perform memory circuit design, characterization, simulations, PPA optimization, bit-cell and periphery IC design, and methodology development while collaborating across technology domains to meet high-performance, low-power requirements on advanced CMOS processes.

The Semiconductor Manufacturing Engineer provides operational support for high volume fabrication facilities, optimizing processes, defining requirements, and collaborating with stakeholders to enhance manufacturing efficiency.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.