Jobs at Intel

Support capitalization process for front-end and back-end foundry activities, drive month-end close and reporting, build financial workflows and automation, perform variance root-cause analysis, evaluate capex and financing, and deliver ad hoc KPI and decision-support analysis.

Design and implement CPU logic and RTL, participate in architecture/microarchitecture, optimize for power/performance/area/timing, write/verify RTL, document microarchitectural specs, and support SoC integration and customers.

Develop long-term capacity strategies and production capacity models for foundry operations. Analyze operational data, optimize equipment schedules and layouts, forecast build plans, and collaborate cross-functionally to improve factory efficiency, reduce cost, and support capital and capacity decisions.

Develop and implement reference designs using Foundational IP, execute full SoC physical design flow from RTL to GDS, run IP QA flows, script and automate design/debug flows, build IP-level quality checks, collaborate with EDA vendors and internal IP teams, and apply data analytics/AI-ML to improve processes and quality.

Validate and QA Intel PDKs across process nodes and EDA flows by developing and running regression test suites, creating layout and circuit test cases, automating regressions, debugging failures, and performing pre- and post-layout simulations and parasitic extraction comparisons.

Implement custom IP and SoC physical design from RTL to GDS: synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power integrity, verification and signoff. Analyze results, recommend fixes, optimize power/frequency/area, develop methodology and automation, and collaborate cross-functionally using industry-standard EDA tools.

Perform full-chip and IP physical implementation from RTL to GDS, including synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power/noise analysis, verification/sign-off, and methodology automation to optimize power, performance, and area for manufacturable SoC designs.

The AI Research Engineer/Scientist will develop state-of-the-art neural network compression algorithms for optimizing inference within the OpenVINO ecosystem, focusing on Deep Learning model optimization and software development.

Diagnose and resolve silicon failures through fault isolation and lab testing. Use probing and automated test systems to identify root causes, collaborate with test, design, and process teams, develop debug tools/methodologies, and recommend design/process quality improvements to support product reliability and time-to-market.

Lead design analysis and methodology for memory blocks and datapath subsystems for high-speed, low-power CPUs. Enable memory methodologies to meet >5GHz, work with layout/floorplanning, implement back-end features, perform memory post-silicon analysis, and apply static timing and statistical variation expertise.

Design, develop, integrate, test, deploy, and support full-stack web and standalone applications for lab and fab operations; apply secure, maintainable software engineering practices; collaborate with cross-functional teams and customers; use Agile and CI/CD practices and AI-assisted tools to deliver production-ready solutions.

Provide executive-level administrative support to multiple leaders: manage complex calendars, coordinate domestic and international travel and visas, prepare expense reports, plan departmental events, maintain SharePoint/Teams and office resources, use enterprise purchasing and finance systems, and partner with senior administrative staff.

Lead design and delivery of full‑stack, production‑quality software for Intel lab and fab operations. Provide technical leadership, mentor junior developers, collaborate with cross‑functional teams, engage stakeholders to gather requirements, and apply Agile, CI/CD, and secure engineering practices. Use AI‑assisted tools to improve productivity and drive solutions from concept through deployment and support.

Lead verification of complex SoC designs: define verification strategy, develop reusable UVM/OVM testbenches, run emulation and system simulation, debug pre-silicon issues, create security-focused tests, improve verification infrastructure, collaborate with architects/RTL teams, and mentor engineers to ensure functionality, performance, and security.

Lead Intel Foundry pre-silicon Design Quality and Reliability team to develop and deploy reliability methodologies, tools, and flows. Mentor engineers, partner with cross-functional and customer/EDA teams, implement metrics and root-cause analysis, and drive solutions that ensure design quality and reliability across Intel silicon technologies.

Responsible for functional verification of IP logic, developing verification plans, running simulations, debugging issues, and collaborating with various engineering teams.

As an NPI Integrator, manage technology transfers and integration processes, analyze data, improve quality and yield, and collaborate with teams to ensure successful project outcomes.

As a DFT Design Engineer, you will enhance test coverage and manufacturability, developing DFT architectures and working with cross-functional teams to ensure testing of silicon solutions.

This role involves improving supply chain processes, managing suppliers, conducting analysis for cost control, and ensuring quality standards in semiconductor manufacturing.

Develop full-stack software solutions for automation applications, collaborating with cross-functional teams, ensuring functionality, and providing technical support for manufacturing processes.